Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2008-11-13
2011-11-22
Lindsay, Jr., Walter L (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S018000, C257SE21521
Reexamination Certificate
active
08062910
ABSTRACT:
A sample that is processed to remove a top layer, e.g., using chemical mechanical polishing or etching, is accurately measured using multiple models of the sample. The multiple models may be constrained based on a pre-processing measurement of the sample. By way of example, the multiple models of the sample may be linked in pairs, where one pair includes a model simulating the pre-processed sample and another model simulating the post-processed sample with a portion of the top layer remaining, i.e., under-processing. Another pair of linked models includes a model simulating the pre-processed sample and a model simulating the post-processing sample with the top layer removed, i.e., the correct amount of processing or over-processing. The underlying layers in the linked model pairs are constrained to have the same parameters. The modeling process may use a non-linear regression or libraries.
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Feng Ye
Liu Zhuan
Lindsay, Jr. Walter L
Mustapha Abdulfattah
Nanometrics Incorporated
Silicon Valley Patent & Group LLP
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