Measure-controlled delay circuits with reduced phase error

Details Measure-controlled delay circuits with reduced phase error Measure-controlled delay circuits with reduced phase error

2007-10-02

2007-10-02

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S141000

Reexamination Certificate

active

10892805

ABSTRACT:
Measure-controlled delay (MCD) circuits include a measure circuit and sample circuit for synchronizing an output clock to an input clock. In response to triggering of the measure circuit, sample circuits sample outputs of a measure delay array. Sample reset logic prevents output of the output clock when any of a predetermined one or more of the samples correspond to a particular logic value (i.e., logic “1” or “0”). For example, sample reset logic may prevent an MCD circuit from providing the output clock when a sample taken from the earliest sampling point of the measure delay array corresponds to logic “1.” The MCD circuit may then provide the output clock in response to a subsequent triggering for which a sample taken from the earliest sampling point is logic “0.” Phase error of the output clock is thereby reduced. MCD circuits improve response to process, voltage and temperature (PVT) variations.

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