Measure-controlled delay circuit with reduced playback error

Details Measure-controlled delay circuit with reduced playback error Measure-controlled delay circuit with reduced playback error

2006-07-11

2006-07-11

Tran, Khai (Department: 2611)

Pulse or digital communications

Synchronizers

C375S359000

Reexamination Certificate

active

07076012

ABSTRACT:
A timing control circuit for synchronizing an output clock signal with an input clock signal includes a pulse generator, a measure delay array, a measure circuit, and a forward delay array. The pulse generator is configured to receive a delay clock signal generated based on the input clock signal and generate a pulse, the pulse having a falling edge corresponding to a rising edge of the delay clock signal. The measure delay array is coupled to the pulse generator to receive the pulse. The measure circuit is configured to determine a position of the pulse within the measure delay array corresponding to a rising edge of the input clock signal. The forward delay array is configured to receive the input clock signal and delay the input clock signal based on the position determined by the measure circuit to generate the output clock signal. A method for synchronizing an output clock signal with an input clock signal includes receiving a delay clock signal generated based on the input clock signal. A pulse is generated having a falling edge corresponding to a rising edge of the delay clock signal. The pulse is propagated through a measure delay array. A position of the pulse within the measure delay array corresponding to a rising edge of the input clock signal is determined. The input clock signal is delayed based on the position determined by the measure circuit to generate the output clock signal.

REFERENCES:
patent: 6198326 (2001-03-01), Choi et al.
patent: 6930525 (2005-08-01), Lin et al.
patent: 2004/0039955 (2004-02-01), Gomm
patent: 2004/0041606 (2004-03-01), Kirsch

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