Means to reduce the PLL phase bump caused by a missing clock...

Details Means to reduce the PLL phase bump caused by a missing clock... Means to reduce the PLL phase bump caused by a missing clock...

2007-05-04

2010-10-19

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000, C327S157000, C327S158000, C327S161000

Reexamination Certificate

active

07816958

ABSTRACT:
A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and applied to the charge pump during a first period. The detection of the pulse-width limited signal is used to generate a first slew signal that is also pulse-width limited and applied to the charge pump during a second period. The detection of the first slew signal is used to generate a second slew signal that is also pulse-width limited and applied to the charge pump during a third period. The amount of current supplied by the charge pump during the second charging period is equal to a sum of currents withdrawn by the charge pump during the first and third time periods.

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