Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-01-08
2004-07-06
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185010, C365S185330, C257S315000, C257S316000, C438S201000, C438S211000, C438S257000
Reexamination Certificate
active
06760258
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of fabricating a low voltage programmable and erasable FLASH EEPROM and the method of programming and erasing this device.
(2) Description of the Prior Art
Flash EEPROM memories are widely used in the electronics industry. Many applications require the ability to change and retain data after removing the system power. Flash EEPROM offers this capability.
Referring now to
FIG. 1
, a cross sectional representation of a partially completed prior art integrated circuit device is shown. A Flash EEPROM memory cell of the prior art is depicted. A semiconductor substrate
10
is shown. Shallow Trench Isolations (STI)
14
are formed in the semiconductor substrate
10
to isolate the memory from surrounding cells. A control and floating gate stack has been fabricated overlying the semiconductor substrate
10
. The control and floating gate stack comprises a tunneling oxide layer
18
overlying the semiconductor substrate
10
. A floating polysilicon gate
22
overlies the tunneling oxide layer
18
. An interpoly dielectric layer
26
overlies the polysilicon floating gate
22
. A polysilicon control gate
30
overlies the interpoly dielectric layer
26
. A drain junction
31
is formed in the semiconductor substrate
10
. A source junction
32
is formed in the semiconductor substrate
10
A substrate contact junction
33
is also formed in the semiconductor substrate
10
. The junctions, polysilicon layers, and oxide layers are all formed by conventional processes.
The Flash EEPROM memory cell operates essentially as an MOS transistor with a variable threshold voltage (V
t
). The state of the threshold voltage (high or low) determines the logical state of the memory cell (for example, binary 0 or 1). The voltage threshold of the memory cell depends upon the charge held on the polysilicon floating gate. Assuming that an n-channel device has been constructed, a sufficient positive voltage bias on the control gate (V
G
) with respect to the substrate (V
SUB
), will cause a conductive channel to form at the surface of the semiconductor substrate
10
. The difference between the gate and substrate voltages is called V
GSUB
. If a voltage delta also exists between the drain junction and the source junction (V
D
-V
S
, or V
DS
), then current will flow through the channel. However, if the threshold voltage were such that V
t
exceeded V
GSUB
, then a conductive channel would not form. Current would not flow from drain to source though the V
DS
bias existed. Sense circuitry in a memory device utilizing FLASH EEPROM cells determines the state (low V
t
or high V
t
) of the cells by measuring whether or not current flows through the cell when the control gate is selected.
As stated, the presence of charge on the floating gate directly affects the threshold voltage V
t
of the cell. The control gate and floating gate are essentially two capacitors in series. Therefore, when a voltage is effected across the control gate to the substrate (V
GSUB
), this voltage is divided between the two capacitors. If a significant charge (positive or negative) exists on the floating gate, this charge cannot escape (under normal, low voltage conditions). Therefore, the charge impacts the voltage division. For example, the presence of a significant negative charge on the floating gate (electrons), will partially offset a positive charge on the control gate (holes) so that the substrate surface underlying the tunnel oxide sees a lower potential. This lower potential requires that fewer electrons be attracted to the substrate surface. The effect of the negative charge on the floating gate is to increase the threshold voltage V
t
required to turn the cell ON.
To change the state of the cell, charge must be added or subtracted from the polysilicon floating gate. The path for adding or subtracting charge (holes or electrons) is through the thin tunneling oxide
18
. The tunneling oxide is formed, by thermal growth or deposition, as a thin layer of silicon dioxide.
When electrons are added to the floating gate, this is typically called programming the cell. When holes are added to the floating gate, this is called erasing the cell. The method used to program the cell typically involves creating a large control gate to substrate voltage (V
GSUB
) of 10 volts or greater. In most cases, the substrate is grounded, therefore, +10 volts or greater must be applied to the control gate. In addition, the source junction is grounded (V
S
) and the drain junction is biased to the low voltage supply of between about +3 volts to about +5 volts. In this condition, a sufficient bias exists to cause avalanche or hot electron injection
34
near the drain junction
31
and into the polysilicon floating gate
22
. Fowler-Nordheim Tunneling also takes place in the programming scenario. Alternatively, to discharge or erase the cell, the control gate voltage (V
GSUB
) must be biased to −10 volts or greater. The source voltage (V
SSUB
) is biased to the low voltage supply of between about +3 volts to about +5 volts. The drain voltage (V
SSUB
) is left floating. Now, electrons cross from the polysilicon floating gate
22
to the source junction
32
to erase the cell by Fowler-Nordheim Tunneling.
Note that the drain junction
31
is typically more shallow and more highly doped than the source junction
32
. This allows the drain junction to avalanche breakdown at a lower voltage which somewhat reduces the large programming and erasing voltage (V
pp
) required to change the logical state of the cell. The large V
pp
makes integration of the memory cells more difficult. The large voltage requires either that an external voltage supply must be added to the system or that a charge pumping circuit be added to the integrated circuit. Either alternative is expensive. The use of the higher voltage in the circuit also requires that a thicker gate oxide be used in the circuitry that is exposed to this voltage. Again, this is expensive due to added processing complexity.
Several prior art approaches deal with Flash EEPROM devices and programming methods. U.S. Pat. No. 4,884,239 to Ono et al teaches a method to erase EPROM cells where a small source to substrate reverse bias eliminates source to substrate current flow. A large drain to source reverse bias is created to create a current reverse avalanche that injects hot holes into the floating gate to erase the cell. U.S. Pat. No. 5,457,652 to Brahmbhatt discloses a method to program and erase an EEPROM. The substrate is grounded. For programming, a +12 volt bias is applied to the control gate. For erasing, a −10 volt bias is applied to the control gate. U.S. Pat. No. 5,659,504 to Bude et al teaches a device and programming method for an EEPROM. The device uses a shallow drain and a halo or p-pocket drain. Programming and erasing is controlled by the drain to source bias with neither floating. Drain to source current is used to program or erase the cell through channel hot electron injection. The p-pocket drain is used to increase hot electron injection from the channel current.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating a Flash EEPROM memory cell in the manufacture of integrated circuits.
A further object of the present invention is to provide a method of fabricating a Flash EEPROM memory cell with a reduced gate to substrate programming voltage.
A yet further object of the present invention is to provide a method of fabricating a Flash EEPROM memory cell with a reduced programming voltage comprising the features of: implanting a shallow and abrupt drain junction, implanting an angled pocket counter-doped junction adjacent to the drain junction, and implanting a deeper and less abrupt source junction.
Another further object of the present invention is to provide a method of fabricating a Flash EEPROM
Chan Tze Ho Simon
Lin Yung-Tao
Chartered Semiconductor Manufacturing Ltd.
Huynh Andy
Nelms David
Pike Rosemary L. S.
Saile George O.
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