Fishing – trapping – and vermin destroying
Patent
1990-06-14
1992-03-10
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437228, H01L 2176
Patent
active
050949721
ABSTRACT:
An integrated circuit device is fabricated upon a semiconductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.
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"A Variable-Size Shallow Trench Isolation (STI) Technology with Difused Sidewall Doping for Submicron CMOS", by B. Davari, C. Koburger, T. Furukawa, Y. Taur, W. Noble, A. Megdanis, J. Warnock, J. Mauer, in the Institute of Electrical & Electronic Engineers Publication No. CH2528-8/88/000-0092, Proceedings of the 1988 IEDM Conference held in San Francisco, pp. IEDM 88-92 to IEDM 88-95.
"A New Planarization Technique, Using a Combination of RIE and Chemical Mechanical Polich (CMP)", by B. Davari, C. Koburger, R. Schultz, J. Warnock, T. Furukawwa, M. Jost, W. Schwittek, M. Kerbaugh, J. Mauer.
Ahn Sung T.
Pierce John M.
Chaudhuri Olik
Fourson G.
Linguiti Frank M.
Murray William H.
National Semiconductor Corp.
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