Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
1999-01-20
2001-11-20
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
C702S057000, C702S062000
Reexamination Certificate
active
06321168
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to making a gate (a smallest circuit component) a library, and particularly, a technique for measuring and predicting a power consumption characteristic of a gate library for a gate level simulator.
(2) Description of the Prior Arts
An estimate of a power consumption at an actual chip in a stage of designing a chip has formerly been executed as described below: treating a circuit as a connected relation on a level of each element among capacity, resistance, diode, current supply, voltage supply and the like; in addition, representing this connected relation by a library and a net list; thereunder, converting these into a relational formula between a current and a voltage; solving the relational formula between a current and a voltage through an input into a circuit by using an iterative method; and using a circuit simulator for estimating a value of a current and a voltage inside a circuit.
However, time required for the simulation increases in proportion to an input signal change column wherein a signal of ON, OFF relates to a wiring which is input from outside.
In a large-scale circuit wherein the number of transistors increases and a connection is complicated, the relational formula between a current and a voltage is complicated, whereby the time increases experientially exponentially on average.
Consequently, such a method can not be applicable to the large-scale circuit.
As an LSI is getting on a large scale in recent years, an estimate of a power consumption in the LSI has generally been executed on a level of a group of transistors and a cell, namely, a gate level simulation.
It is necessary for the estimate of a power consumption on a gate level simulation to measure and predict beforehand by a circuit simulator a corresponding relation (a relation between a circuit input and a power consumption) between an input logical change and a power consumption, which is consumed at a logical gate when the input logical change occurs, at a logical gate which is the smallest component on a gate level simulation, and thereby make the values a library.
A method of measuring and calculating a power consumption by a circuit simulator in all input logical changes regarding an input into a logical gate has generally been used for calculating the relation between a circuit input and a power consumption However, in the method, since each gate of N input gates can usually have two logical values, an input logic is made 2{circumflex over ( )}N (the N-th power of 2). A change for the input logic is also made 2{circumflex over ( )}N, and since one of them is the same as the input logic, an input logical change of (2{circumflex over ( )}N)×(2{circumflex over ( )}N−1) is necessary in total. Accordingly, when the number of an input terminal at a logical gate increases, time required for an estimate of a power consumption (time required for measuring and calculating actually) is very long.
In recent years, a large-scale logical gate having a large-scale circuit and many input terminals is increasing, such as a complicated combination logical gate for using a logical composition tool efficiently and a multiplier for recycling a design. Consequently, the problem is that time required for an estimate of a power consumption increases in estimating a power consumption at such a logical gate.
For instance, in a measuring system for a power consumption parameter (hereinafter referred to as ‘CB-Power’), which is written in ASP-DAC '97 3G. 1 CB-Power A Hierarchical Cell-Based Power Characterization and Estimation Environment for Static CMOS Circuits, such a method is used as described below: calculating a power consumption for all input signal changes which change an output wiring of such partial circuits as AND, OR which are used in a logical gate; making a calculated power consumption a library beforehand; and calculating a power consumption at a logical gate comprising a combination of these partial circuits by the sum of a power consumption corresponding to an input change in the partial circuit, which is caused by an input change at the logical gate.
In this method, the number of input changes in a partial circuit and partial circuits for measuring and calculating a power consumption is reduced in measuring a power consumption covering a plurality of logical gates by measuring and calculating a power consumption in only an input change which changes an output from a partial circuit among all input changes which have the possibility of an input into a partial circuit in making a, power consumption in a partial circuit a library beforehand for applying to a plurality of logical gates as well as applying a power consumption in the above-mentioned partial circuit to a partial circuit having the same constitution as the above-mentioned partial circuit in a circuit diagram of a logical gate, whereby the reduction of the time for a circuit simulation is intended.
For instance, in a circuit shown in
FIG. 1
, it is presumed that it takes a minute to calculate a power consumption in each of partial circuits P
01
and P
02
for an input logical change and two minutes to calculate a power consumption in the whole circuit.
Then, in a calculation time of a power consumption in the whole circuit, an input logical change has twelve sorts of (2{circumflex over ( )}2)×(2{circumflex over ( )}2−1) in a general method because of two input gates.
Since the calculation of a power consumption is executed in each circuit for two minutes, it takes twenty-four minutes in total.
Meanwhile, in a method of CB-Power, since only an input logical change which changes an output is processed, an input logical change having the sorts of (the number of input logical values for outputting logic 0)×(the number of input logical values for outputting logic 1)×2 is necessary in each partial circuit.
A circuit shown in
FIG. 1
is divided into partial circuits P
01
and P
02
shown in
FIG. 2
by a process as described in detail below, and a logical relation between input and output in a partial Circuit P
01
is indicated in
301
of
FIG. 3 and a
logical relation between input and output in a partial circuit P
02
is indicated in
302
of
FIG. 3
, therefore, the number of input logical changes necessary for the partial circuit P
01
is six sorts of 1×3×2 and the number of input logical changes necessary for the partial circuit P
02
is thirty sorts of 3×5×2.
Accordingly, in a method of CB-Power, since the calculation of a power consumption is executed for a minute in each of input logical changes having six sorts for the partial circuit P
01
and thirty sorts for the partial circuit P
02
, it takes thirty-six minutes.
That is, in a method of CB-Power, the time required for calculating a power consumption is longer than in a general method in the case of a logical gate.
However, in the case of a hundred kinds of partial circuits, if each one kind of a partial circuit is used twice in the whole circuit, it takes 2,400 minutes of 24×100 in a general method, however, it takes only 1,800 minutes of 36×100/2 in a method of CB-Power.
If each one kind of a partial circuit is used three times in the whole circuit, it takes 1,200 minutes, and if four times, it takes 900 minutes.
In a gate array library which is intended for a gate array in a mode wherein a logic element made on a thin film silicon on a substrate is connected with a wiring, since kinds of a logic element tends to be reduced and a size (width and height) of a transistor (strictly, a transistor as an element, however, it is referred to as merely ‘a transistor’ in this specification) used at the logic element tends to be made uniform in order to use the logic element efficiently, eventually, partial circuits having the same characteristic and constitution are frequently used at a plurality of logical gates. Consequently, in a method of CB-Power, the time required for calculating a power consumption characteristic can be redu
Bui Bryan
Hoff Marc S.
Matsushita Electric - Industrial Co., Ltd.
Parkhurst & Wendel L.L.P.
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