Means for reducing spurious frequencies in a direct frequency sy

Details Means for reducing spurious frequencies in a direct frequency sy Means for reducing spurious frequencies in a direct frequency sy

1978-01-03

1980-01-22

Heyman, John S.

328 14, H03K 1332

Patent

active

041852478

ABSTRACT:
Spurious frequencies are eliminated in a direct frequency synthesizer by means of a feed forward correction circuit. The improved direct frequency synthesizer of the invention includes a series adder, clocked register, a D/A converter and a phase corrector. The adder is inputted by a digital control increment and the output of the register. The system clock frequency is divided down by a smoothing counter that in part controls the phase of the output signal. Spurious frequencies are manifested by overflow of the register. The register overflow is converted to an analog signal by the D/A converter. The system output is provided by a voltage controlled oscillator that is controlled by an amplifier which is responsive to both the smoothing counter output and the analog output of the D/A converter. Additionally, the D/A converter is sampled twice for every cycle of output frequency, resulting in a doubling of the output frequency for a given D/A converter.

REFERENCES:
patent: 3882403 (1975-05-01), Gerken
patent: 3973209 (1976-08-01), Nossen et al.
patent: 3976945 (1976-08-01), Cox
patent: 4011516 (1977-03-01), Heimbigner et al.

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