Means for providing a graceful power shut-down capability in a m

Details Means for providing a graceful power shut-down capability in a m Means for providing a graceful power shut-down capability in a m

1991-10-22

1994-11-22

Bowler, Alyssa H.

Boots, shoes, and leggings

395575, 395750, 3642289, 3642853, 364264, 364DIG1, 371 55, 371 91, 371 14, G06F 130

Patent

active

053676971

ABSTRACT:
A multiprocessor computer system includes first processors, second processors, a system management means for performing system management functions, including detecting pending power shut-downs and sending power shut-down messages addressed to each of the first processors warning of pending power shut-downs, and a system bus for communication between the first and second processors and the system management means, including the communication of pending power shut-down messages. The first processors include interrupt handling means responsive to pending power shut-down messages for executing power shut-down routines for placing the first processors into a known state before power termination, but the second processors inherently do not include a power shut-down capability. In each of the second processors, a power shut-down means is provided to place the second processors in a known state before a power termination, including a bus monitor connected from the system bus and responsive to any power shut-down message addressed to a first processor for generating an output indicating the occurrence of a power shut-down message to a first processor. The second processor also includes non-maskable interrupt logic connected from the power shut-down message output of the bus monitor and responsive to the power shut-down message output of the bus monitor for generating a non-maskable interrupt output to the second processor. The second processor is in turn responsive to a non-maskable interrupt output of the non-maskable logic for querying the non-maskable logic to determine the nature of the interrupt, and responsive to the indicated occurrence of a power shut-down message to any first processor for executing a power shut-down routine for placing the second processor in a known state before the termination of power.

REFERENCES:
patent: 4260854 (1981-04-01), Kolodny et al.
patent: 4914576 (1990-04-01), Zelley et al.
patent: 5155842 (1992-10-01), Kubin

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