Means for coordinating asynchronous main store accesses in a mul

Details Means for coordinating asynchronous main store accesses in a mul Means for coordinating asynchronous main store accesses in a mul

1973-12-26

1976-03-30

Malzahn, David H.

Communications: electrical

Digital comparator systems

G06F 918

Patent

active

039478238

ABSTRACT:
A unique control circuit that maintains the addressability to an invalidated page frame until execution is completed for all current instructions in all CPUs of a multiprocessing system which uses demand-paging and virtual addressing.
A support method is also disclosed which provides an asynchronous sequence of operations for each CPU in the multiprocessing system to maintain the page in the invalidated page frame available to all CPUs and until their current instruction execution is completed. The last CPU to complete its execution moves the page, if modified, out of the page frame.

REFERENCES:
patent: 3421151 (1969-01-01), Quosig et al.
patent: 3647348 (1972-03-01), Smith et al.
patent: 3665404 (1972-05-01), Werner
patent: 3716837 (1973-02-01), Waddell
patent: 3825904 (1974-07-01), Burk et al.
patent: 3828327 (1974-09-01), Berglund et al.

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