Means for control limits for delay locked loop

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

327 2, 327148, 327149, 327157, 327158, 327276, 327261, H03K 5159

Patent

active

056636652

ABSTRACT:
A delay lock loop having an improved delay element which results in a two-fold improvement in the operation of the delay lock loop. Firstly, it guarantees that the phase detector portion of the delay lock loop will yield the correct phase differential. Secondly, it eliminates the possibility of a harmonic lock condition from occurring.

REFERENCES:
patent: 4855683 (1989-08-01), Trouder et al.
patent: 5120990 (1992-06-01), Koker
Mark G. Johnson and Edwin L. Hudson, A Variable Delay Line PLL for CPU-Coprocessor Synchronization, Oct., 1988, IEEE Journal of Solid-State Circuits, vol. 23, No. 5.
Mel Bazes and Roni Ashuri, A Novel CMOS Digital Clock and Data Decoder, Dec., 1992, IEEE Journal of Solid-State Circuits, vol. 27, No. 12.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Means for control limits for delay locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Means for control limits for delay locked loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Means for control limits for delay locked loop will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-312098

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.