Means and method of reducing the number of masks utilized in fab

Details Means and method of reducing the number of masks utilized in fab Means and method of reducing the number of masks utilized in fab

1974-12-13

1986-12-23

Smith, Jr., David

357 40, 357 71, H01L 2706

Patent

active

046315691

ABSTRACT:
A plurality of integrated circuit wafers each having a plurality of cells disposed in a rectilinear array with the yield distribution of usable cells varying from wafer to wafer but in which there is a common yield distribution of at least Y usable cells or portions thereof in corresponding locations on N wafers (where Y and N are integers); a layer of electrical insulation that exposes the pads of the Y common yield distribution usable circuits to a second level of metalization which is formed into conductors by a first pad relocation mask which is common to the N wafers for effectively routing the exposed pads of the Y usable cells to master pattern circuit locations; and a layer of electrical insulation formed over the second level of metalization having master pattern vias formed therethrough which expose the pads at master pattern cell locations to a top layer of metalization formed into a common or master pattern of interconnects which interconnect the cells into the specific circuit type by a master pattern mask common to the Y wafers and a plurality of other wafers to be connected into the specific circuit type.

REFERENCES:
patent: 3303400 (1967-02-01), Allison
patent: 3423822 (1969-01-01), Davidson et al.
patent: 3434020 (1969-03-01), Ruggiero
patent: 3508325 (1970-04-01), Perry
patent: 3518751 (1970-07-01), Waters et al.
patent: 3585712 (1971-06-01), Boncuk
patent: 3618201 (1971-11-01), Makimoto et al.
patent: 3641661 (1972-02-01), Canning
patent: 3835530 (1974-09-01), Kilby

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