Means and method for error detection and correction of digital d

Communications: electrical – Digital comparator systems

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G06F 1112

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active

039822265

ABSTRACT:
Apparatus for detecting and correcting errors in one or two tracks of a multi-bit, multi-track data group which includes an error correction character (ECC). The received data group is simultaneously stored and applied to an ECC generator which operates upon each data byte according to an operator B such that an error correction character ECC is reproduced. The ECC is of such a nature that another application of operator B produces a new character termed an error vector E. If all of the received data characters are correct all data bits of the error vector E will be zero. The error vector may be regressively operated on by the operator B and sequentially compared to a locally-generated parity vector P.sub.n. If single track is in error its identity is determined by the number of cycles by operator B necessary to obtain an error vector identical to the parity vector. If more than one track is in error, and identified by means of pointers, the tracks and the difference therebetween are identified and a divisor generated to operate on the previously-obtained combination of error and parity vectors. The resulting dividend comprises an error vector for a least significant track, and is applied through a correction matrix to correct that track. The least significant track error vector is also combined with locally-generated parity to produce an error correction vector for the most significant track, which is applied to a correction matrix to invert erroneous bits of data in the relevant track of uncorrected information received from the storage register.

REFERENCES:
patent: 3675200 (1972-07-01), Bossen et al.
patent: 3697948 (1972-10-01), Bossen
patent: 3745526 (1973-07-01), Hong et al.
patent: 3745528 (1973-07-01), Patel
patent: 3800281 (1974-03-01), Devore et al.
patent: 3851306 (1974-11-01), Patel
patent: 3868632 (1975-02-01), Hong et al.

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