Means and method for disabling access to a memory

Details Means and method for disabling access to a memory Means and method for disabling access to a memory

1981-07-10

1984-05-01

Larkins, William D.

Registers

Coded record sensors

Particular sensor structure

235487, 235492, 357 45, 357 85, 357 84, 365 94, 365189, 29583, 29591, H01L 2704, G11C 1140

Patent

active

044464754

ABSTRACT:
An integrated circuit chip having a digital memory is provided wherein direct access to at least a portion of the memory is prevented. Contact pads having coupling lines to couple the contact pads to the memory bus are provided. A security code can be programmed into a portion of the memory during wafer probe and test. When the integrated circuit chip is removed from the wafer the coupling lines between the contact pads and the memory bus are destroyed since the coupling lines are made to extend off of the chip.

REFERENCES:
patent: 3484341 (1969-12-01), Devitt
patent: 3544861 (1970-12-01), Kooi
patent: 4004133 (1977-01-01), Hannan
patent: 4105156 (1978-08-01), Dethloff
patent: 4144523 (1979-03-01), Kaplit
patent: 4219827 (1980-08-01), Kaiser
Shultis, IBM Technical Discl. Bulletin, vol. 13, No. 7, Dec. 1970, p. 1793.
Brickman, IBM Technical Discl. Bulletin, vol. 13, No. 7, Dec. 1970, pp. 1927-1928.

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