MDS decoder circuit with high voltage suppression of a decouplin

Details MDS decoder circuit with high voltage suppression of a decouplin MDS decoder circuit with high voltage suppression of a decouplin

1986-03-10

1989-03-07

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Sync/clocking

365230, 307449, G11C 800, G11C 8000, H03K 19094, H03K 1920

Patent

active

048113042

ABSTRACT:
A dynamic random access memory device having common signal lines to transmit row address signals and column address signals, uses change-over switches to transfer those signals to a row decoder. Voltage suppression circuitry limits high voltage applied to decoupling transistors provided at decoder outputs. An MOS transistor used as a voltage suppression device between the decoupling transistor and a word line activating transistor transfers word line activating signals.

REFERENCES:
patent: 4289982 (1981-09-01), Smith
patent: 4417329 (1983-11-01), Mezawa et al.
patent: 4490628 (1984-12-01), Ogura
"A 90 ns 1 Mb DRAM with Multi-Bit Test Mode", Masaki Kaumanoya et al., '85 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 240-241, p. 352.

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