Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Patent
1993-07-26
1995-07-11
Chin, Stephen
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
375346, H03D 100, H04L 2706
Patent
active
054328209
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a maximum likelihood decoding method, and to a device implementing the method, for conducting maximum-likelihood decoding on an input signal subject to intersymbol interference.
Demand for larger capacity recording precipitates a requirement for higher density recording in a magnetic disk apparatus, for example. Accordingly, because read-out signals are subject to intersymbol interference to a great extent, making the task of waveform equalization difficult to achieve (e.g., to force equalization in such a case induces a greater high-band noise), a high error rate is observed in a decoding operation using peak detection or level identification. One approach, to make improvements in an error rate in decoding, is to conduct maximum-likelihood decoding on a read-out signal subject to intersymbol interference or a received signal subject to intersymbol interference in a data transmission system, using a Viterbi decoder for decoding the selected most probable sequence of the assumed data sequences.
BACKGROUND ART
A decoding system of a known magnetic recording apparatus has a construction such as the one shown in FIG.1. Therein, 11 represents a magnetic head for reproducing recorded data from a recording medium such as a magnetic disk, 12 an amplifier, 13 an equalizer, 14 a pulse shaper, 15 a phase locked loop (PLL), 16 a equalizer, 17 an A/D converter (A/D), and 18 a Viterbi decoder.
A signal reproduced by the magnetic head 11 is amplified by the amplifier 12, subjected to equalizing amplification by the equalizers 13 and 16 consisting of filters, for example, and has its noise removed. The pulse shaper 14 generates pulses by peak detection, and a clock signal is obtained by means of the phase locked loop 15, which signal is synchronous with a read-out signal. This clock signal is then used as a sampling clock signal of the A/D converter 17; the read-out signal, equalized by the equalizer 16, is furnished to the A/D converter 17 and sampled thereby, responsive to the one-bit-rate sampling clock signal from the phase locked loop 15, so as to be converted to a digital signal. Sample values of the read-out signal, thus converted to a digital signal, all furnished to the Viterbi decoder 8 so as to be decoded by maximum-likelihood decoding.
Viterbi decoder is known as a maximum-likelihood decoder for convolution codes and comprises, as shown in FIG. 2, a distributor 21, ACS circuits 22-1-22-4, a path memory 23, a normalizing circuit 24 and a path selector 25, the distributor 21 being used in computing a branch metric value for distribution to ACS circuits 22-1-22-4. Given that the constraint length of convolution codes is k, the number of ACS circuits to be provided is 2.sup.k-1. The provision of 4 ACS circuits provided in FIG. 2 indicates a case in which the constraint length k=3.
Each of the ACS circuits 22-1-22-4 comprises an adder (A), a comparator (C) and a selector (S), in which the adder (A) adds the branch metric value and the previous metric value, the comparator (C) compares those values, and the the selector (S) selects the smaller metric value as the path metric value of the survivor path. The path selection signal thereof is stored in the path memory 23. The path memory 23, containing a number of stages of path memory cells which is as many as 4-5 times that of the constraint length k, stores the signal as the survivor path. The output of the final stage is furnished to the path selector 25, after which the path corresponding to the smallest path metric value is selected. The decoded output is thus obtained. When the number of digits becomes so large as to cause an overflow in computing the path metric value, the normalizing circuit 24 normalizes the path metric value. When employing a Viterbi decoder of this configuration in decoding a signal subject to intersymbol interference, the ACS circuits create a new path metric value by adding the previous path metric value to the output obtained by squaring the difference between the assumed sample
REFERENCES:
patent: 4631735 (1986-12-01), Qurechi
patent: 4953183 (1990-08-01), Bergmans et al.
patent: 5150379 (1992-09-01), Baugh et al.
Aikawa Takashi
Kasai Kiichirou
Mizoshita Yoshifumi
Mutoh Hiroshi
Sugawara Takao
Chin Stephen
Fujitsu Limited
Kobayashi Duane
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