Maximum density interconnections for large scale integrated circ

Details Maximum density interconnections for large scale integrated circ Maximum density interconnections for large scale integrated circ

1977-11-02

1980-12-30

Wojciechowicz, Edward J.

357 67, 357 68, H01L 2348

Patent

active

042426987

ABSTRACT:
A microelectronic integrated circuit having first and second levels of thin-film metallization separated by an insulation layer is provided with a system for electrical interconnections between metallization levels, at selected locations, without requiring extra spacing between metal paths, in either the first or second levels. Maximum circuit density is thereby permitted, with no restriction on the placement of interconnection vias. Circuit layout is greatly simplified because all metal paths have uniform widths and minimum spacings, achieved with the use of vias that are "oversized" in both the transverse and longitudinal directions. Consequently, it is required that second level metal differ in composition from first level metal, and be patterned with an etchant that does not attack first level metal.

REFERENCES:
patent: 3936865 (1976-02-01), Robinson
patent: 4042953 (1977-08-01), Hall
patent: 4151545 (1979-04-01), Schnepf et al.

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