Maximized data space in shared memory between processors

Electrical computers and digital processing systems: interprogra – Interprogram communication using shared memory

Reexamination Certificate

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Details

C711S147000, C711S148000, C711S149000, C709S214000, C709S215000, C709S216000

Reexamination Certificate

active

06912716

ABSTRACT:
A technique and apparatus for efficiently and flexibly utilizing shared memory as a full duplex mailbox for both data and payload information. The invention allows payload messages of varying lengths to be passed in contiguous memory space, allowing an interrupt service routine (ISR) or other process to easily and quickly read or cache the passed payload data. In a disclosed embodiment, a processor-to-processor mailbox is formed using a shared memory (e.g., a dual port RAM). The shared memory is separated into three main portions: a processor1to processor2fixed portion, a processor2to processor1fixed portion, and an unallocated dynamic portion. Importantly, the other direction of the mailbox is located starting at the highest address of the shared memory, and works toward the lowest address of the shared memory. Preferably, write access for payload messages and other generally longer messages are dynamically allocated in the unallocated dynamic portion for use in either mailbox. For messages passed in mailbox1, i.e., from processor1to processor2, the memory in the unallocated dynamic portion is allocated in a lowest to highest address direction. Conversely, for messages passed in mailbox2, i.e., from processor2to processor1, the memory in the unallocated dynamic portion is allocated in a highest to lowest address direction.

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patent: 5802351 (1998-09-01), Frampton

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