Maximally negative signed fractional number multiplication

Details Maximally negative signed fractional number multiplication Maximally negative signed fractional number multiplication

2005-10-04

2005-10-04

Malzahn, D. H. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06952711

ABSTRACT:
A method and processor for multiplying two maximally negative fractional numbers to produce a 32-bit result are provided. Operands are fetched from a source location for operation of a multiplication operation. Result outputs corresponding to a maximally negative result are detected. The detection of a maximally negative result indicates that the operands are two maximally negative fractional numbers. Maximally negative results are corrected to produce a maximally positive result. Result output are fractionally aligned and sign extended for accumulation in an accumulator.

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