Maximal deversity combining interference cancellation using sub-

Details Maximal deversity combining interference cancellation using sub- Maximal deversity combining interference cancellation using sub-

1995-05-26

1996-02-20

Blum, Theodore M.

Communications: directive radio wave systems and devices (e.g.,

Directive

Utilizing correlation techniques

342381, 342375, G01S 316, G01S 328

Patent

active

054933072

ABSTRACT:
A sidelobe canceler includes a main antenna, an array of sub-antennas, a subtractor having a first input connected to the main antenna, a main-array processor and M sub-array processors. The main-array processor multiplies the outputs of the sub-antennas with weight coefficients using correlations between the sub-antenna outputs and the subtractor output and combines the multiplied signals into a signal, which is coupled to the second input of the subtractor. The signal-to-noise ratio of the subtractor output is maximized by an adaptive matched filter. Each sub-array processor multiplies the sub-antenna outputs with weight coefficients using correlations between the sub-antenna outputs and a decision signal. The multiplied signals are summed to produce an output of each sub-array processor, which is combined with the outputs of the other sub-array processors into a first diversity-combined signal, the latter being combined with the matched filter output to produce a second diversity-combined signal. Intersymbol interference is removed by an adaptive equalizer from the second diversity-combined signal according to a decision error so that the decision signal is produced and applied to the sub-array processors. Different amounts of delay are introduced to the outputs of (M-1) of the sub-array processors so that the output of the i-th sub-array processor is delayed by (i-1).tau., where i=2,3, . . . , M, and different amounts of delay are introduced to the decision signals applied to (M-1) of the sub-array processors so that the decision signal applied to the j-th sub-array processor is delayed by (M-j).tau., where j=1,2, . . . , M-1. The total amounts of delay associated with each of the M sub-array processors is equal to (M-1).tau..

REFERENCES:
patent: 4720712 (1988-01-01), Brookner et al.
patent: 4771289 (1988-09-01), Masak
patent: 5369412 (1994-11-01), Tsujimoto

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