Matrixed magnetic bubble memories

Static information storage and retrieval – Magnetic bubbles – Disposition of elements

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365 12, 365 15, G11C 1908

Patent

active

040818616

ABSTRACT:
A magnetic bubble memory organization comprising a plurality of magnetic bubble memory chips arranged in rows and columns to form a matrix. Each chip has a plurality of memory locations for storing magnetic bubbles, selectively operable components for transferring magnetic bubbles out of and into memory locations for the retrieval and storage of information, a selectively operable replicator and annihilator of magnetic bubble information transferred out of memory locations on the chip, a generator selectively operable for producing magnetic bubbles for storage in memory locations on the chip, and a detector for sensing the presence of magnetic bubbles transferred out of memory locations and for providing an electrical output signal in response to the detection thereof. First transfer electrical control signals are respectively commonly applied to the first transfer components on all chips in each of the respective columns of the matrix for their simultaneous actuation. Similarly second transfer electrical control signals are respectively commonly applied to the second transfer components on all chips in each of the respective columns of the matrix for their simultaneous actuation. Replicate and annihilate electrical control signals are respectively commonly applied to the replicator and annihilator on all chips in each of the respective rows of the matrix for their simultaneous actuation. Generate control signals are respectively commonly applied to the generators on all chips in each of the respective rows of the matrix for their simultaneous actuation. The movement of magnetic bubbles in all chips is synchronized. A single circuit commonly connecting the detector of each chip in the matrix conveys retrieved information out of the matrix. Thus, the memory locations of any magnetic bubble memory chip in the matrix may be selectively accessed for the storage and retrieval of information with a minimum number of different control signal sources and conductors for all the chips in the matrix and only a single output circuit.

REFERENCES:
patent: 3737882 (1973-06-01), Furuoya
patent: 3750154 (1973-07-01), Almasi
patent: 3751597 (1973-08-01), Bonyhard
patent: 3792450 (1974-02-01), Bogar et al.
patent: 3838407 (1974-09-01), Juliussen
patent: 3944991 (1976-03-01), Murakami

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