Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
1999-12-23
2003-09-16
Parker, Kenneth (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S147000
Reexamination Certificate
active
06621536
ABSTRACT:
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a matrix wiring substrate and a liquid crystal display substrate, and more particularly to a matrix wiring substrate with bus lines and other lines disposed in the row and column directions, and to a liquid crystal display substrate having such a wiring structure.
b) Description of the Related Art
FIG. 6
is a schematic plane view of a conventional thin film transistor (TFT) substrate of an active matrix type liquid crystal panel. In the image display area of the surface of a glass substrate, a plurality of gate bus lines
1
are disposed extending in the row direction and a plurality of drain bus lines
2
are disposed extending in the column direction. The gate and drain bus lines
1
and
2
are insulated from each other at each cross point by an insulating film.
Although not shown in
FIG. 6
, near at each cross point between the gate and drain bus lines
1
and
2
, a TFT and a pixel electrode are disposed.
In an area other than the image display area of the surface of the glass substrate
19
, e.g., in the area along the left side edge shown in
FIG. 6
, a gate bundling line
15
is disposed extending in the column direction. The gate bundling line
15
is connected to a signal input terminal
28
. Each gate bus line
1
is connected at its left end to the gate bundling line
15
. The gate bundling line
15
, signal input terminal
28
and gate bus lines
1
are formed at the same time by patterning the same conductive film.
In an area other than the image display area of the surface of the glass substrate
19
, e.g., in the area along the bottom side edge shown in
FIG. 6
, a drain bundling line
10
is disposed extending in the row direction. The drain bundling line is connected to a signal input terminal
25
. Each drain bus line
2
is connected at its lower end to the drain bundling line
10
. The drain bundling line
10
, signal input terminal
25
and drain bus lines
2
are formed at the same time by patterning the same conductive film.
A display test is performed by driving all pixels at the same time by applying a TFT control signal to the signal input terminal
28
and an image data signal to the signal input terminal
25
.
Before shipping displays, a laser beam is applied to each connection portion between the gate bus line
1
and gate bundling line
15
to disconnect each gate bus line
1
from the gate bundling line
15
. In the similar manner, each drain bus line
2
is disconnected from the drain bundling line
10
.
Referring to
FIG. 6
, distances to pixels from the signal input terminal
25
are different. If the electric resistance of the drain bundling line
10
is high, a signal transmission delay at a pixel remote from the signal input terminal
25
becomes large. Therefore, the voltage at the pixel electrode may not rise a desired voltage during the period while each pixel TFT is made conductive by the signal applied to the gate bus line
11
. In such a case, an expected brightness of the pixel cannot be obtained.
Similar phenomenon may occur in the case of the gate bundling line
15
.
As the signal transmission delay of the gate bundling line
15
becomes large, a gate voltage waveform at a pixel TFT remote from the signal input terminal
28
rises gently. Therefore, a conduction period of TFT may become shorter than an expected period.
If the gate and drain bundling lines
15
and
10
are made thick, the wiring resistance can be reduced. However, as the wiring width is made wider, a large area is occupied by these wiring lines and the integration degree is lowered.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a matrix wiring substrate capable of reducing the resistance of bundling lines to be formed on the substrate.
According to one aspect of the present invention, there is provided a matrix wiring substrate comprising: a substrate having a principal surface; a plurality of first bus lines formed in a first wiring layer above the principal surface of said substrate and extending in a row direction of the principal surface; a first bundling line formed in the first wiring layer and extending in a column direction of the principal surface, said first bundling line being connected to one end portion of each of said first bus lines; a plurality of second bus lines formed in a second wiring layer different from the first wiring line above the principal surface of said substrate and extending in the column direction of the principal surface, each of said second bus lines crossing each of said first bus lines; a second bundling line formed in the second wiring layer and extending in the row direction of the principal surface, said second bundling line being connected to one end portion of each of said second bus lines; a first insulating film disposed between the first wiring layer and the second wiring layer to electrically insulate the first and second wiring layers; a first auxiliary line formed in the first wiring layer along said second bundling line; and an interlayer connection member for electrically connecting said first auxiliary line to said second bundling line or said second bus lines, wherein each of said first bus lines is cut at a point near a connection portion between each of said first bus lines and said first bundling line, and each of said second bus lines is cut at a point near a connection portion between each of said second bus lines and said second bundling line.
The first auxiliary bundling line is disposed along the second bundling line and both the lines are electrically connected. Therefore, as compared to a second bundling line formed by a single wiring layer, the wiring resistance can be reduced.
As above, the electric resistance can be reduced by forming a bundling line of at least a two-layer structure.
REFERENCES:
patent: 5019001 (1991-05-01), Abe et al.
patent: 5377030 (1994-12-01), Suzuki et al.
patent: 5532615 (1996-07-01), Kondo et al.
patent: 5668032 (1997-09-01), Holmberg et al.
patent: 5796449 (1998-08-01), Song
patent: 5825439 (1998-10-01), Noriyama
patent: 5949502 (1999-09-01), Matsunaga et al.
patent: 6005647 (1999-12-01), Lim
patent: 6100949 (2000-08-01), Kim
patent: 6211076 (2001-04-01), Song et al.
patent: 6215541 (2001-04-01), Song et al.
patent: 6310667 (2001-10-01), Nakayoshi et al.
patent: 6429908 (2002-08-01), Lim
patent: 4 03249624 (1991-11-01), None
patent: 03-290623 (1991-12-01), None
Fujitsu Display Technologies Corporation
Greer Burns & Crain Ltd.
Parker Kenneth
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