Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2000-04-13
2003-06-17
Paladini, Albert W. (Department: 2827)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S760000, C361S783000, C257S787000
Reexamination Certificate
active
06580620
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for reproducing a printed circuit board (PCB) for semiconductor packages, and more particularly to a matrix type PCB for semiconductor packages having a structure including a plurality of PCB units arranged in a matrix array having at least two rows in such a fashion that the mold runner gates of adjacent PCB units respectively arranged in adjacent rows while being arranged in the same column communicate with each other by an integrate mold runner, thereby being capable of allowing an increased number of PCB units to be simultaneously processed in each process involved in the fabrication of semiconductor packages, so that a great improvement in productivity is achieved.
2. Description of the Prior Art
Generally, a PCB is a circuit board adapted to transmit electrical signals from a semiconductor chip mounted thereon to an external unit and from the external unit to the semiconductor chip. Such a PCB is fabricated by laminating conductive thin films over upper and lower surfaces of a resin substrate made of a glass fiber reinforced thermosetting resin composite, patterning the conductive thin films in accordance with well-known photolithography processes, thereby forming circuit patterns on the upper and lower surfaces of the resin substrate, electrically connecting those circuit patterns to each other by via holes, and coating solder masks, made of a polymer resin, on the upper and lower surfaces of the resin substrate at desired regions, respectively.
The PCB having the above mentioned structure is called a “single-layer PCB”. Recently, a multi-layer PCB has been proposed which is formed by laminating a plurality of single-layer PCB structures, each having a resin substrate and a pair of conductive circuit patterns, to form a multi-layer PCB structure. In such a multi-layer PCB structure, adjacent conductive circuits of adjacent layers are electrically connected by conductive via holes.
Referring to
FIG. 1
, a conventional PCB strip having the above mentioned structure is schematically illustrated.
As shown in
FIG. 1
, the PCB strip, which is denoted by the reference numeral
10
′, includes a resin substrate
6
′ having a rectangular strip shape. A plurality of conductive circuit patterns (not shown) are formed on each of upper and lower surfaces of the resin substrate
6
′. Solder masks
5
′ are also formed on the upper and lower surfaces of the resin substrate
6
′, respectively, in order to protect the conductive circuit patterns formed on the upper and lower surface of the resin substrate
6
′ from the surrounding environment while preventing those conductive circuit patterns from being short-circuited. A plurality of mold runner gates
2
′ are formed on the upper surface of the resin substrate
6
′. Each mold runner gate
2
′ is arranged at one corner of a region corresponding to one of PCB units
10
a
′ longitudinally aligned with one another along the PCB strip in the form of a strip. Each mold runner gate
2
′ is plated with gold (Au) or palladium and adapted to guide a melted encapsulating resin of high temperature and high pressure to a resin encapsulation region defined on an associated one of the PCB units
10
a
′. The resin encapsulation region of each PCB unit
10
a
′ is defined by a resin encapsulation line
4
′. The melted encapsulating resin is introduced into the resin encapsulation region of each PCB units
10
a
′ through an associated one of the mold runner gates
2
′, and then cured, thereby forming a resin encapsulate encapsulating a semiconductor chip mounted on the PCB unit
10
a
′ along with bonding wires. After the formation of the resin encapsulates, the surplus encapsulating resin cured in each mold runner gate
2
′ serving as a resin introduction passage is subjected to a degating or deculling process so that it is removed. Since the gold or palladium coated over the mold runner gates
2
′ exhibits a bonding force to the encapsulating resin considerably lower than the bonding force to the resin substrate or the solder mask, the surplus encapsulating resin cured in each mold runner gate
2
′ can be easily removed without causing the solder mask and circuit patterns to be damaged.
For the formation of the resin encapsulates, an upper mold and a lower mold (not shown) are used which are engaged with each other. At the region defined by the resin encapsulation line
4
′ in each PCB unit
10
a
′, an associated one of cavities defined in the upper mold is arranged. The melted encapsulating resin fills each cavity, and is then cured, thereby forming a resin encapsulate. In
FIG. 1
, the reference numeral
3
′ denotes package unit singulation lines along which the PCB strip
10
′ is cut into individual semiconductor packages respectively corresponding to the PCB units after the resin encapsulate formation so that those semiconductor packages are separated from one another.
A plurality of spaced pin holes
7
′ are formed at each longitudinal edge of the PCB strip
10
′ in order to allow an easy feeding of the PCB strip
10
′ between adjacent processes.
The conductive circuit patterns of adjacent PCB units
10
a
′ in the PCB strip
10
′ are electrically connected. Accordingly, the electroplating process for the conductive circuit patterns of all PCB units
10
a
′ can be conducted in a single pass. After the completion of the electroplating process, slots
1
′ are perforated through respective portions of the PCB strip
10
′ where the conductive circuit patterns of adjacent PCB units
10
a
′ are electrically connected, thereby causing those conductive circuit patterns to be disconnected. As a result, it is possible to easily conduct an open/short circuit test for each PCB unit
10
a
′. It is also possible to prevent the PCB strip
10
′ from being bent due to a thermal expansion coefficient difference between the resin substrate
6
′ and the circuit patterns when being subjected to high temperature processes conducted in the fabrication of semiconductor packages.
However, the above mentioned conventional PCB strip
10
′ has a problem in that there is a great limitation on the number of semiconductor packages fabricated from one PCB strip. For instance, only seven semiconductor packages can be fabricated from the PCB strip shown in FIG.
1
. Although active attempts have been made in a variety of fields associated with the fabrication of semiconductor packages to reduce the manufacturing costs, there is a limitation on the reduction of manufacturing costs insofar as the PCB strip
10
′ having the above mentioned structure is used. The above mentioned PCB strip structure also involves a problem of a low productivity in that there is a great limitation on the number of PCB units processed per process in the fabrication of semiconductor packages.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a matrix type PCB for semiconductor packages having a structure capable of allowing an increased number of PCB units to be simultaneously processed in each process involved in the fabrication of semiconductor packages, thereby achieving a great improvement in productivity.
A second object of the invention is to provide a matrix type PCB for semiconductor packages having a structure capable of allowing an increased number of PCB units to be simultaneously molded in a resin encapsulate molding process, thereby achieving a great improvement in the efficiency of the resin encapsulate molding process.
A third object of the invention is to provide a matrix type PCB for semiconductor packages having a structure capable of easily and reliably removing surplus encapsulating resin materials cured in mold runner gates and integrate mold runners in accordance with a degating and/or deculling process without surface damage to the PCB.
A fou
Amkor Technology Inc.
Bever Hoffman & Harms
Dinh Tuan
Paladini Albert W.
Parsons James E.
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