Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
1998-06-08
2003-07-15
Hjerpe, Richard (Department: 2774)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S099000
Reexamination Certificate
active
06593918
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to driving of a matrix type panel and more particularly to driving of a matrix type panel using a liquid crystal.
A matrix-type panel has display elements (pixels) arranged in a matrix formation. Data is written into the panel while the horizontal lines of the panel are sequentially selected one by one. The data is applied to the selected horizontal line on which a line image defined by the applied data is formed. Generally, such a matrix-type panel employs a liquid crystal. For example, a type of matrix-type liquid crystal panel has switching elements which are formed to thin film transistors (TFT) located at the pixels arranged in the matrix formation. Another type of matrix-type liquid crystal panel has a matrix electrode structure called CS-ON-GATE.
2. Description of the Related Art
FIG. 1
is a block diagram of a liquid crystal display device using a matrix-type liquid crystal display panel as described above. The device shown in
FIG. 1
includes a panel
10
, a data driver
12
, a gate driver
14
and a timing control circuit
16
. The panel
10
has display elements arranged in a matrix formation. The data driver
12
receives data R (red), G (green) and B (blue) (hereinafter also referred to as RGB data) to be written into a horizontal line, and outputs the received RGB data to the panel
10
. The gate driver
14
selects the horizontal line on the panel
10
. The timing control circuit
16
provides the data driver
12
and the gate driver
14
with given timing signals (which will be described later). The RGB data, which is gradation data, can be analog image data or digital image data. The analog image data is ac data which drives the liquid crystal in an ac formation. The digital data is gradation data consisting of a plurality of bits, and conversion of ac data is carried out within the data driver
12
.
FIG. 2
is a block diagram of an internal structure of the gate driver
14
, which is made up of an inverter
18
, an n-stage shift register
20
and AND gates
22
1
through
22
n
where n is an integer. The gate driver
14
receives timing signals &PHgr;x, STV and /OEG. The timing signal &PHgr;x is a shift clock signal, and the timing signal STV is a start pulse signal which starts the gate driver
14
operating. The timing signal /OEG is an output enable signal which enables the gate driver
14
. The shift register
20
latches the start signal STV when the shift clock &PHgr;x rises while the start pulse signal STV is high, and outputs a high-level signal to the AND gate
22
1
. The AND gate
22
1
is connected to, for example, the first line of the panel
10
, and outputs a high-level signal when the output enable signal /OEG is low. The output signal of the AND gate
22
1
is applied to the panel
10
as a driving signal, and the first line of the panel
10
is selected. As described above, the shift operation is carried out each time the shift clock &PHgr;x rises, and the panel
10
is sequentially selected one line by one line.
FIG. 3
is a block diagram of an internal structure of the data driver
12
shown in FIG.
1
. The data driver
12
includes an m-stage shift register
24
, switches
26
1
-
26
m
, and data latches
28
1
-
28
m
where m is an integer and may be equal to or not equal to n. The switch
26
m
and the data latch
28
m
are not shown in FIG.
3
. The data driver
12
receives timing signals SIO, CLK and LE generated by the timing control circuit
16
. The timing signal SIO is a start pulse signal which starts the data driver
12
operating. The timing signal CLK is a clock signal. The timing signal LE is a latch control signal. The shift register
24
latches the start pulse signal SIO when the clock signal CLK rises while the start pulse signal SIO is high, and shifts the start pulse signal SIO each time the clock signal CLK rises. Hence, the switches
26
1
,
26
2
and
26
3
are sequentially selected and data R, G and B externally supplied are latched. Hence, data equal to one horizontal line is latched, and thereafter the latch control signal LE is switched to the high level. Hence, the data equal to one horizontal line is output to the panel
10
at one time.
The timing control circuit
16
produces the above-mentioned timing signals from a vertical synchronizing signal V-SYNC and a horizontal synchronizing signal H-SYNC.
A “free run” occurs in the matrix-type panel display device. The free run indicates a state in which a timing signal to be applied is not applied temporarily. More particularly, inputting of at least one of the vertical synchronizing signal V-SYNC and the horizontal synchronizing signal H-SYNC is temporarily stopped.
FIG. 4
is a timing chart showing operations of the structures shown in
FIGS. 1 through 3
. In
FIG. 4
, the first pulse P
1
of the vertical synchronizing signal V-SYNC, and then the horizontal synchronizing signal H-SYNC is input. Thereafter, a state is encountered in which both the vertical synchronizing signal V-SYNC and the horizontal synchronizing signal H-SYNC are stopped. Such a state is the free run. The timing control circuit
16
, which produces the timing signals from the vertical and horizontal synchronizing signals V-SYNC and H-SYNC, is designed to continue to produce the timing signals STV, &PHgr;x and /OEG even if the synchronizing signals are stopped. Hence, a dc component is prevented from flowing in the panel
10
. For instance, if the liquid crystal display device displays an image reproduced by a video tape player or recorder, the RGB data is applied from the video tape player. In this case, if the reproduction of the video tape player is paused, the free-run state takes place and the vertical synchronizing signal V-SYNC and the horizontal synchronizing signal H-SYNC are stopped. However, writing of data can be enabled because the timing control circuit
16
continues to produce the timing signals.
Thereafter, a pulse P
2
of the vertical synchronizing signal V-SYNC is input and the horizontal synchronizing signal H-SYNC is input. Pulse #
1
of the start pulse signal STV is produced in response to the pulse P
1
of the vertical synchronizing signal V-SYNC by the timing generating circuit
16
. Similarly, pulse #
2
of the start pulse signal STV is produced in response to the pulse P
2
. In response to pulse #
1
, the horizontal lines are sequentially scanned one by one in synchronism with the shift clock &PHgr;x. Pulse #
2
is produced when a certain horizontal line is being scanned. In this case, the scanning of the first horizontal line is started in response to pulse #
2
of the start pulse signal STV. That is, two horizontal lines respectively responsive to pulses #
1
and #
2
are concurrently scanned. Hence, an image which is to be displayed on an upper portion of the plane is displayed on an intermediate portion of the plane starting from a horizontal line which is currently driven in response to pulse #
1
.
The free run causes a problem when a wide display is realized on the panel
10
.
FIG. 5
shows a case where a wide display having an aspect ratio of 16:9 is realized on the panel
10
of a normal size having an aspect ratio of 4:3. In this case, black is displayed on upper and lower display portions (dotted areas) of the panel
10
, and the wide display is realized on the remaining display area having an aspect ratio of 16:9. When the free run occurs, the timing control circuit
16
is not provided with the vertical synchronizing signal V-SYNC and the horizontal synchronizing signal H-SYNC. Hence, the timing control circuit
16
cannot recognize which portion of the panel
10
is being scanned. If the supply of the vertical synchronizing signal V-SYNC and the horizontal synchronizing signal H-SYNC is restarted, an image may instantaneously displayed on the black areas. Such an instantaneous display may be distractive to the person who watches the panel
10
.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a matrix-type
Kishida Katsuhiko
Miyamoto Hirofumi
Onodera Toshiya
Taguchi Yoshihisa
Tanaka Katsunori
Fujitsu Limited
Greer Burns & Crain Ltd.
Hjerpe Richard
Laneau Ronald
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