Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-09-20
2003-05-06
Wu, Xiao (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000
Reexamination Certificate
active
06559824
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a matrix type image display device having a structure for stabilizing the operation of a shift register that transfers a digital signal in synchronism with a clock signal, more particularly a structure for preventing an operational error due to indefiniteness of an internal state when power is supplied.
BACKGROUND OF THE INVENTION
The present invention is directed to various image display devices. Here, the present invention is explained by particularly illustrating an active matrix type liquid crystal display device as an example. However, the present invention is not necessarily limited to this example, and is applicable to devices and systems in other fields for the same purposes.
A known conventional image display device is an active matrix drive-type liquid crystal display device. As shown in
FIG. 43
, this liquid crystal display device includes a pixel array
101
, a scanning signal line drive circuit
102
, a data signal line drive circuit
103
, a pre-charge circuit
104
, and a control circuit
105
.
The pixel array
101
includes a number of scanning signal lines GL (GL
j
, GL
j+1
, . . . ) and data signal lines SL (SL
j
, SL
j+1
, . . . ) that cross each other, and pixels
101
a
(shown as PIX in
FIG. 43
) arranged in a matrix form. As shown in
FIG. 5
, the pixel
101
a
is composed of a pixel transistor SW as a switching element and a pixel capacitor C
P
including a liquid crystal capacitor C
L
(and a storage capacitor C
S
, if necessary).
The data signal line drive circuit
103
samples an input image signal DAT (data) in synchronism with a control signal such as a clock signal SCK, amplifies it, if necessary, and outputs the resultant signal to each data signal line SL. The scanning signal line drive circuit
102
sequentially selects scanning signal lines GL in synchronism with a control signal such as a clock signal GCK and controls the opening and closing of the pixel transistor SW in the pixel
101
a
so as to write and hold in each pixel
101
a
the image signal DAT output to each data signal line SL. The pre-charge circuit
104
is a circuit provided, if necessary, to support the output of the image signal to the data signal lines SL, and preliminarily charges the data signal lines SL before outputting the image signal DAT from the data signal line drive circuit
103
to the data signal lines SL.
By the way, in the conventional active matrix type liquid crystal display device as described above, an amorphous silicon thin film formed on a transparent substrate such as a glass substrate is used as a material of the pixel transistor SW. Besides, the scanning signal line drive circuit
102
and data signal line drive circuit
103
are formed by external integrated circuits (IC) respectively.
On the other hand, in recent years, in order to meet demands for an improvement of the driving force of the pixel transistor SW for an increase in the size of the screen, a reduction of the mounting cost of the drive ICs and the mounting reliability, a technique for fabricating the pixel array
101
and drive circuits
102
and
103
in a monolithic form by the use of a polycrystalline silicon thin film was developed and reported. Moreover, in order to further increase the size of the screen and reduce the cost, attempts to form the pixel array
101
and drive circuits
102
and
103
by a polycrystalline silicon thin film on the glass substrate at a process temperature of not higher than a distortion point (about 600° C.) of glass have been made.
For example, a liquid crystal display device shown in
FIG. 44
employs a structure in which the pixel array
101
, scanning signal line drive circuit
102
and data signal line drive circuit
103
are mounted on a glass substrate
107
, and the control circuit
105
and power supply circuit
106
are connected to them.
Next, the structure of the data signal line drive circuit
103
will be explained. As the data signal line drive circuit
103
, a dot sequential driving-type and line sequential driving-type used according to the type of an input signal have been known. In general, in a polycrystalline silicon TFT panel in which the drive circuits and pixels are formed to be monolithic, a point sequential driving-type drive circuit is often used because of the simpleness of the circuit structure. Therefore, the dot sequential driving-type scanning signal line drive circuit
102
and data signal line drive circuit
103
will be described here.
For example, as shown in
FIG. 45
, the dot sequential driving-type data signal line drive circuit
103
includes a shift register
111
for sequentially transferring a start signal SST at the timing of the clock signal SCK and inverted clock signal /SCK (the inverted signal of SCK). In this data signal line drive circuit
103
, the result of a logical operation of output pulses of adjacent two flip-flops
111
a
in the shift register
111
is obtained by, for example, a NAND gate
111
c
, and an output pulse of the NAND gate
111
c
that has passed through the buffer circuit
112
is supplied as a control signal for a sampling switch
113
. The sampling switch
113
fetches the input image signal DAT and outputs it to the data signal lines SL
n
(n=1, 2, 3, 4, . . . ) when it is turned on by the control signal.
However, the logic circuit such as the NAND gate
111
c
is provided, if necessary. In other words, if the logical operation is not necessary, the image signal DAT is sampled according to the output pulse of the flip-flop
111
a.
As shown in
FIG. 46
, the scanning signal line drive circuit
102
includes a shift register
111
for sequentially transferring a start signal GST at the timing of the clock signal GCK and inverted clock signal /GCK (the inverted signal of GCK). In this scanning signal line drive circuit
102
, the result of a logical operation of output signals of adjacent two flip-flops
111
a
in the shift register
111
is obtained by, for example, a NAND gate
111
c
, and a scanning signal is obtained. More specifically, the result of a logical operation of the output pulse of the NAND gate
111
c
and an inverted signal /GEN of an enable signal GEN supplied from the control circuit
105
is obtained by, for example, a NOR gate
114
, and the result is output as a scanning signal via a buffer circuit
115
to the scanning signal lines GL
n
(n=1, 2, 3, 4, . . . ).
However, if the logical operation is not necessary, the output of the flip-flop
111
a
is used as a scanning signal.
As described above, in both of the data signal line drive circuit
103
and scanning signal line drive circuit
102
, the shift register
111
for sequentially transferring a pulse signal is used. This shift register
111
employs a structure in which a plurality of flip-flops
111
a
are connected in series, and is driven by the clock signal SCK, inverted clock signal /SCK, clock signal GCK and inverted clock signal /GCK as shown, for example, in
FIGS. 45 and 46
.
The flip-flop shown in
FIG. 47
is composed of one inverter
121
and two clocked inverters
122
and
123
. The clock signal CK and inverted clock signal /CK input to the two clocked inverters
122
and
123
have opposite phases. In adjacent flip-flops, the input clock signals have opposite phases. In general, this type of flip-flop is referred to as a D-type flip-flop.
For example, as shown in
FIG. 48
, other data signal line drive circuit
103
is formed by an S-R flip-flop
111
b
which is driven by a set signal for causing the inside to be an active state and a reset signal for causing the inside to be an inactive state.
As shown in
FIGS. 48 and 49
, in an S-R flip-flop
111
b
, the inverted clock signal /CK (/SCK) input according to the control by an output signal G of the flip-flop
111
b
in the preceding stage is used as the set signal, and the output signal of the flip-flop
111
b
in the succeeding stage is used as the reset signal RES. The clock signals of opposite phases are input to adjacent flip-flops
111
b
, respectively. In t
Brownlow Michael James
Cairns Graham Andrew
Kubota Yasushi
Maeda Kazuhiro
Washio Hajime
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