Matrix times matrix multiplier

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G06F 752

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active

048414697

ABSTRACT:
A circuit for the multiplication of the elements of a multiplicand matrix represented by first digital signals by the elements of a multiplier matrix represented by second digital signals. A multiplicand line is provided for every row of the multiplicand matrix and the individual sections (L11. . . L14) o f these multiplicand lines are connected to bit-associated circuits (bit planes) (BP1. . . BP4). Every bit plane contains the partial product stages (1, 2, 3) which are allocated to the bits of the second digital signals having a defined significance, and also contain an iterative circuit composed of adders (4, 5) and time delay elements (6, 7, 8) in an alternating arrangement.

REFERENCES:
patent: 4686645 (1987-08-01), McCanny et al.
patent: 4697247 (1987-09-01), Grinberg et al.
patent: 4719588 (1988-01-01), Tatemichi et al.
patent: 4763365 (1973-10-01), Seitz
patent: 4787057 (1988-11-01), Hammond

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