Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1998-11-24
2004-08-10
Yao, Kwang Bin (Department: 2663)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S387000
Reexamination Certificate
active
06775275
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a matrix switch method and device and, more particularly, to a high-speed data matrix switch method and device which are used for a switch unit or cross-connect apparatus in large-capacity communication.
In a future switch unit or cross-connect apparatus used for large-capacity communication, it is expected that switching of large-capacity data on the several 10 Gbit/s order will be required. In this case, a matrix switch device used for these apparatuses is required to have the function of switching high-speed data with a signal speed of several Gbit/s at each input/output terminal. A significant challenge for such an apparatus is to suppress a deterioration in the waveform of high-speed data, and more specifically, time jitter, in the matrix switch device.
Such a high-speed matrix switch device has recently been under development. For example, a technique associated with a space-division matrix switch is disclosed in “1 Gbit/s, 32×32 HIGH-SPEED SPACE-DIVISION SWITCHING MODULE FOR BROADBAND ISDN USING SST LSIs”, IEE ELECTRONICS LETTERS, Vol. 25, No. 13, pp. 831-833, June 1989.
FIG. 9
shows a conventional matrix switch device.
Referring to
FIG. 9
, eight input data are input to a latch
91
. The eight signals are then input from the latch
91
to an 8×8 matrix switch
92
. The 8×8 matrix switch
92
is made up of eight 8:1 switches
93
connected in parallel. The eight output signals from the matrix switch
92
are input to a latch
94
. External clock signals
95
are input to the latch
91
through a variable delay circuit
97
, and clock signals
96
are input to the latch
94
.
The operation of the conventional matrix switch device having the above arrangement will be described next.
All the eight input data are regenerated and reshaped by the clock signals
95
having the same frequency and phase and the latch
91
. Since the input data greatly deteriorate in waveform after passing through the 8×8 matrix switch
92
, the data are reshaped again by the latch
94
using the clocks signals
96
having the same frequency as that of the clock signals
95
.
This conventional device properly operates with a time jitter amount of 80 ps or less up to 2.2 Gbit/s input data.
In this conventional matrix switch device, if the input data are not synchronized with each other, the signal time phase difference between the respective input data becomes indefinite. In such a case, since waveform shaping cannot be performed by the first latch
91
even by adjusting the clock signals
95
, wave-shaping in the first and second latches
91
and
94
cannot be performed.
Consequently, a considerable deterioration in waveform occurs in the matrix switch device, and the device cannot be applied to high-speed data switching.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a matrix switch method and apparatus which can perform high-speed switching processing for a plurality of parallel input data.
In order to achieve the above object, according to the present invention, there is provided a matrix switch method comprising the steps of extracting pieces of timing information synchronous with signal speeds of input data parallelly input to N (N is a positive integer) input terminals, switching and outputting the respective input data to N output terminals through a switch, and regenerating output signals from output terminals of the switch by using the pieces of timing information extracted from the corresponding input data.
REFERENCES:
patent: 5081655 (1992-01-01), Long
patent: 5099234 (1992-03-01), Kraker et al.
patent: 5297173 (1994-03-01), Hikmet et al.
patent: 5448192 (1995-09-01), Van De Wiel
patent: 5719862 (1998-02-01), Lee et al.
patent: 5784357 (1998-07-01), Wolker et al.
patent: 5796795 (1998-08-01), Mussman et al.
patent: 63-30093 (1988-02-01), None
patent: 2-179046 (1990-07-01), None
patent: 63-131437 (1998-08-01), None
“1 Gbit/s, 32×32 High -Speed Space-Division Switching Module For Broadband ISDN Using SST LSIS”, IEEE Electronics Letters, vol. 25, No. 13, pp. 831-833.
George Keith M.
NEC Corporation
Yao Kwang Bin
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