Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
1998-10-22
2002-11-05
Sikes, William L. (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S143000
Reexamination Certificate
active
06476897
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to matrix substrates used in liquid crystal devices, and relates to liquid crystal display devices and projection liquid crystal display devices using the matrix substrates.
2. Description of the Related Art
Recent progress in information networks has increased the need for display devices for communication of information, particularly image information. Liquid crystal display devices, which are thin and have an advantage in low electrical power consumption, have attracted considerable attention and are growing as one of the basic industries, similarly to the semiconductor industries. Recently, liquid crystal display devices have mainly been used in 12″ notebook personal computers. In the future, liquid crystal display devices having larger screen sizes will be used in workstations and home televisions, as well as in personal computers. The trends toward increasing scale in liquid crystal display devices, however, demands the introduction of expensive apparatuses for producing such devices. Further, large scale liquid crystal display devices must have extreme electrical characteristics for driving large screens. Thus, production costs increase significantly, that is, in proportion to from the square to the cube of the screen size.
A front- or back-projection system using a small-size liquid crystal display panel recently has attracted attention in which a liquid crystal image is optically enlarged and displayed. Performance and production costs of liquid crystal display devices are improved with size reduction in the devices by the scaling rule as in semiconductors. In TFT liquid crystal display panels, TFTs using polycrystalline Si are being substituted for those using amorphous Si to meet the requirement of small-size TFTs having high driving force. Image signals having a resolution level in the NTSC standard do not require high-speed processing.
A possible TFT liquid crystal display device which can be used to meet such requirements has an integrated structure including a display region and peripheral driving circuits, such as a shift register and a decoder, which are also formed of polycrystalline Si. Polycrystalline Si, however, is not comparable to single crystal Si. When a display of an extended graphics array (XGA) or super extended graphics array (SXGA) class in the resolution standard of computers is designed, for example, the shift register must inevitably be divided into a plurality of segments. Signal noise (ghosting) will occur in the display region corresponding to the boundary between the segments. Countermeasures are required for solving such problems.
Japanese Patent Laid-Open No. 9-73103 discloses a reflection-type liquid crystal device using polycrystalline Si and single crystal Si for solving the degradation problem of the displayed image by a decreased contrast which is caused by reduced reflectance of light because of scattering of light incident on the pixel electrode having surface unevenness in all directions, and insufficient alignment of the alignment film in the rubbing step in the liquid crystal mounting process and thus unsatisfactory alignment of the liquid crystal.
Japanese Patent Laid-Open No. 9-73103 discloses pixel electrodes having smooth surfaces formed by chemical/mechanical polishing (hereinafter referred to as CMP). Each of the resulting pixel electrodes has a mirror surface and all the pixel electrodes lie in the same plane. The smooth surface permits display of high quality images free of random scattering of incident light and insufficient alignment of liquid crystals.
A method for making an active matrix substrate disclosed in Japanese Patent Laid-Open No. 9-73103 will be described with reference to
FIGS. 30A
to
30
H.
FIGS. 30A
to
30
H describe a pixel section. Peripheral circuits such as a shift register for driving a switching transistor in the pixel section can also be simultaneously formed during the formation of the pixel section on the same substrate.
An n-type silicon semiconductor substrate
201
having an impurity concentration of 10
15
cm
−3
or less is subjected to local thermal oxidation to form a LOCOS (local oxidation of silicon) layer
202
, and boron ions are implanted in a dose of approximately 10
12
cm
−2
through the LOCOS layer
202
as a mask to form a p-type well (PWL)
203
being a p-type impurity region having an impurity concentration of 10
16
cm
−3
. The substrate
201
is thermally oxidized to form a gate oxide film
204
having a thickness of 1,000 angstroms or less (FIG.
30
A).
An n-type polysilicon gate electrode
205
is formed by doping phosphorus in an amount of approximately 10
20
cm
−3
, phosphorus ions are implanted onto the entire surface of the substrate
201
in a dose of approximately 10
12
cm
−2
to form an n-type lightly doped drain (NLD)
206
being an n-type impurity region having an impurity concentration of 10
16
cm
−3
. Phosphorus ions are implanted through a patterned photoresist mask in a dose of approximately 10
15
cm
−2
to form source and drain regions
207
and
207
′ having an impurity concentration of approximately 10
19
cm
−3
(FIG.
30
B).
A phospho-silicate glass (PSG)
208
, which is a phosphorus-doped oxide film, is formed as an interlayer on the entire substrate
201
. The PSG film
208
can be replaced with a nondoped silicate glass (NSG)/boro-phospho-silicate glass (BPSG) film or a tetraethoxysilane (TEOS) film. Contact holes are patterned into the PSG film
208
just above the source and drain regions
207
and
207
′. Aluminum is deposited by a sputtering process and then patterned to form an aluminum electrode
209
(FIG.
30
C). It is preferred that a barrier metal composed of Ti or TiN be formed between the aluminum electrode
209
and the source and drain regions
207
and
207
′ so as to improve the ohmic contact characteristics between the aluminum electrode
209
and the source and drain regions
207
and
207
′.
A plasma SiN film
210
with a thickness of approximately 3,000 angstroms, and then a PSG film
211
with a thickness of approximately 10,000 angstroms are formed on the entire substrate
201
(FIG.
30
D). The PSG film
211
is patterned using the plasma SiN film
210
as a dry etching stopper layer so as to leave the separation region between pixels, and then a through hole
212
is patterned just above the aluminum electrode
208
which is in contact with the drain region
207
′ by dry etching (FIG.
30
E).
A pixel electrode
213
with a thickness of approximately 10,000 angstroms or more is formed on the substrate
201
by sputtering or electron beam (EB) deposition (FIG.
30
F). The pixel electrode
213
is composed of a metal film of Al, Ti, Ta or W, or a metal compound film of such a metal. The surface of the pixel electrode
213
is polished by CMP (FIG.
30
G).
An alignment film
215
is formed on the resulting active matrix substrate, and its surface is subjected to alignment treatment such as rubbing. The substrate is bonded with a counter substrate with a spacer (not shown in the drawing) therebetween, and a liquid crystal
214
is injected into the gap to form a liquid crystal device (FIG.
30
H). The counter electrode includes a transparent substrate
220
, a color filter
221
, a black matrix
222
, a common electrode of ITO
223
, and an alignment film
215
, in that order.
The reflection-type liquid crystal device is driven as follows. Peripheral circuits including a shift register which is formed on the substrate
201
by an on-chip process applies a signal potential to the source region
207
and a gate potential to the gate electrode
205
such that the switching transistor in the pixel in an ON state supplies signal charge to the drain region
207
′. The signal charge is accumulated in a pn-junction cavity capacitor formed between the drain region
207
′ and the PWL
203
to impart a potential to the pixel electrode
213
through the alumi
Koyama Osamu
Kurematsu Katsumi
Watanabe Takanori
Nguyen Dung
Sikes William L.
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