Matrix of multiplexed synchronized counters for an integrated ci

Details Matrix of multiplexed synchronized counters for an integrated ci Matrix of multiplexed synchronized counters for an integrated ci

1990-04-12

1991-08-06

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Counter controlled counter

364900, 377 33, G06F 946, G06F 1520

Patent

active

050383558

ABSTRACT:
A matrix of multiplexed synchronous binary counters for an integrated circuit comprising a sequence of m counter cells (CC1, CCm) each provided with an individual data input link (Din.1, Din.m) and an individual data output link (Dout.1, Dout.m), and controlled by means of common links comprising a clock link (Clk) for synchronization, a load link (LOAD), and n select links (LS1 to LSn). Each counter cell (CC) includes n memory cells (CM1 CMn), each organized around a unique memory element (B1 to Bn) which is individually selectable by means of the select links (LS1 to LSn), which cells are connected in parallel between the individual data input link (Din) and the individual data output link (Dout) of the said counter cell (CC), and share a common loop memory element (BR) having its data input connected to the individual data ouput link of the counter cell under consideration (CC) via an incrementation circuit.

REFERENCES:
patent: 4089156 (1978-05-01), Kashio
patent: 4161787 (1979-07-01), Groves et al.
patent: 4195292 (1980-03-01), Puhich
patent: 4477918 (1984-10-01), Nossen et al.
patent: 4489422 (1984-12-01), Paradise et al.
patent: 4713832 (1987-12-01), Hutson
Patent Abstracts of Japan, vol. 6, No. 200 (E-135)[1078], Oct. 9, 1982; & JP-A-57 107 641 (Fujitsu K. K.) 7/5/82.

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