Matrix multiplier circuit

Details Matrix multiplier circuit Matrix multiplier circuit

1991-06-28

1993-07-06

Nguyen, Long T.

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G06F 752

Patent

active

052260020

ABSTRACT:
A matrix multiplier circuit which is based on distributed arithmetic is disclosed. In the conventional matrix multiplier circuit, one row of J elements from a data matrix is multiplied in parallel with K columns of elements from a transform matrix to form one row of elements of an output matrix. In contrast, in the inventive matrix multiplier circuit, N rows of elements from the data matrix are multiplied in parallel with K columns of elements from a transform matrix. Maximum advantage of parallel processing and pipelined processing is achieved if N is the nearest integer to M/J where M is the precision of the elements from the data matrix.

REFERENCES:
patent: 4553220 (1985-11-01), Swanson
patent: 4841469 (1989-06-01), Kuenemund et al.
M. T. Sun et al, "A Concurrent Architecture of VLSI Implementation of Discrete Cosine Transform", IEEE Transactions on Circuits and Systems, vol. CAS-34, No. 8, Aug. 1987, pp. 992-994.
M. T. Sun et al, "VLSI Implementation of a 16.times.16 Discrete Cosine Transform", IEEE Trans. on Circuits & Systems, vol. 36, No. 4, Apr. 1989, pp. 610-617.

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