Matrix multiplication circuit for graphic display

Details Matrix multiplication circuit for graphic display Matrix multiplication circuit for graphic display

1984-05-07

1988-01-12

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 752

Patent

active

047195886

ABSTRACT:
A matrices elements memory is constituted by random access memories, and its addresses are divided into a high address and a low address. The high address specifies areas holding matrix elements, and the low addresses of the matrix elements are designated sequentially bit-by-bit, starting from the least significant bit, so as to enable serial reading. A calculation unit consists of pairs of serial multiplicators which are either used in a cascade connection or independently as independent multiplicators, in order to correspond to the data length of a multiplicand.

REFERENCES:
patent: 3161764 (1964-12-01), Croy
patent: 3763365 (1973-10-01), Seitz
patent: 4044243 (1977-08-01), Cooper et al.
patent: 4254474 (1981-03-01), Copper et al.
patent: 4507748 (1985-03-01), Cotton
patent: 4553220 (1985-11-01), Swanson

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