Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-03-29
2002-11-19
Mengistu, Amare (Department: 2778)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S103000
Reexamination Certificate
active
06483497
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a driving apparatus and a driving method for a liquid crystal display having a plurality of row electrodes and column electrodes. More particularly, the present invention relates to a liquid crystal display or other matrix-type display apparatus suited to using a multiple line selection drive method, and relates specifically to an improvement of primarily the matrix-type display element module, controller, and signal electrode driver circuit.
BACKGROUND OF THE INVENTION
In a simple matrix-type liquid crystal display commonly used for flat panel display devices, the display data from a microprocessor unit (MPU) is typically transferred to the LCD module (the liquid crystal display panel (LCD panel)), the scan electrode drive circuit (Y driver), and the signal electrode drive circuit (X driver) using one of two basic methods: using a matrix-type liquid crystal display element module controller (simply “module controller” below), or using an X driver embedded in RAM.
The module controller method is described first. As with a CRT display apparatus, the module controller connected to the system bus reads the display data from video RAM (VRAM), and sends the data to the LCD module at a high frequency to refresh the display.
In the latter method, a dual port frame memory (built-in RAM) is provided in the X driver. This frame memory is directly accessed by the MPU via the data bus, control bus, or address bus irrespective of the LCD timing to generate the required control signal in the X driver by changing the display data in the frame memory. One scan line equivalent of display data is simultaneously read from the built-in frame memory to refresh the display.
With the module controller method above, VRAM data access and transfer coordinated with the LCD timing must be executed each time the display screen is changed, and it is therefore necessary for the VRAM, module controller, and LCD driver to constantly operate at a high frequency. In addition, the display refresh operation involves operation of the VRAM, module controller, and LCD driver. Operation of an LSI device at a high frequency clock results in through-current flowing to the plural CMOS devices used as circuit elements, increasing the total current consumption. Total current consumption also increases in direct proportion to the size of the LCD panel. In addition, while the VRAM is accessed by both the MPU and the module controller, a high speed clock must be used so that MPU access during the display refresh operation does not collide with module controller access, thus limiting the use of a low frequency operating module controller and limiting the processing ability of the MPU.
Operation at a low frequency clock is possible in the latter method above because there is no relationship between display data transfer and LCD timing. This method thus requires 10-100 times less power than the module controller method. When using a large liquid crystal panel, however, the number of X drivers must be increased.
The number of X driver output terminals is generally a multiple of ten (e.g., 160 pins) and not a power of two (e.g., 2
n
), however, because each RAM device built into the X drivers has an independent address area. When the internal memory of plural X drivers is addressed by the MPU, the MPU finds apparent gaps in the total memory area, and it is usually difficult to maintain a continuous sequence of addresses. As a result, the address coordination process of the MPU must be executed at high speed when the entire display area is changed at one time as during scrolling or panning operations, significantly increasing the processing load on the MPU.
It is, of course, possible to design the X driver ICs to have an exponent-of-two number of output pins, but this would seriously impair system interchangeability because compatibility with the number of electrodes in existing LCD panels would be lost. In addition, use of plural X drivers necessarily increases the number of chip selection buses, and sufficient space for this plural number of X drivers to be installed around the LCD panel must be provided. This reduces the display area ratio of the display panel, and inhibits the potential size reduction of the LCD module. The latter method above is therefore unsuited to large scale liquid crystal panels.
Matrix liquid crystal displays such as, twisted nematic (TN) and super twisted nematic (STN), are known in the art. Reference is made to
FIGS. 21A-21E
and
FIG. 22
in which a conventional matrix liquid crystal display is provided. A liquid crystal panel generally indicated as 1 is composed of a liquid crystal layer
5
, a first substrate
2
and a second substrate
3
for sandwiching the liquid crystal layer
5
therebetween. A group of column electrodes Y
1
-Y
m
are oriented on substrate
2
in the vertical direction and a plurality of row electrodes X
1
-X
n
are formed on substrate
3
in substantially the horizontal direction to form a matrix. Each intersection of column electrodes Y
1
-Y
m
and row electrodes X
1
-X
n
forms a display element or pixel
7
. Display pixels
7
having the open circle indicate an ON state and those pixels having a blank indicate an OFF state.
A conventional multiplex driving based on the amplitude selective addressing scheme is known to one of ordinary skill in the art as one method of driving the liquid crystal cells mentioned above. In such a method, a selected voltage or non-selected voltage is sequentially applied to each of row electrodes X
1
-X
n
individually. That is, a selection voltage is applied to only one row electrode at a time. In the conventional driving method, the time period required to apply the successive selected or non-selected voltage to all the row electrodes X
1
-X
n
is as one frame period, indicated in
FIGS. 21A-21E
as time period F. Typically the frame period is approximate {fraction (1/60)} th of a second or 16.66 milliseconds.
Simultaneously to the successive application of the selected voltage or the non-selected voltage to each of the row electrodes X
1
-X
n
, a data signal representing an ON or OFF voltage is applied to column electrodes Y
1
-Y
m
. Accordingly to turn on a pixel
7
, the area in which the row electrode intersects the column electrode, to the ON state, an ON voltage is applied to a desired column electrode when the row electrode is selected.
Referring specifically to
FIGS. 21A-21E
, a conventional multiplex drive method of a simple matrix type liquid crystal and more specifically the amplitude selective addressing scheme is shown therein.
FIGS. 21A-21C
show the row selection voltage waveforms that is applied in sequence to row electrodes X
1
, X
2
. . . X
n
, respectively. More particularly, in time period t
1
, a voltage pulse having a magnitude of V
1
is applied to row electrode X
1
, and a voltage of zero is applied to electrodes X
2
-X
n
; in time period t
2
, a voltage pulse having a magnitude of V
1
is applied to row electrode X
2
and a voltage of zero is applied to electrodes X
1
and X
3
-X
n
; and in time period t
n
, V
1
is applied to row electrode X
n
and a voltage of zero is to electrodes X
1
-X
n-1
. In other words, a voltage pulse having a magnitude of V
1
is applied to only one row electrode X
i
in time t
i
. Typically, ti is approximately 69 &mgr; seconds and V
1
is approximately 25 volts. As will be apparent to one who has read this description, all of the row electrodes are sequentially selected in time periods t
1
-t
n
or one frame period F.
FIG. 21D
shows the waveform applied to column electrode Y
1
, and
FIG. 21E
shows the synthesized voltage waveform applied to the pixel 7
1,1
formed at the intersection of the column electrode Y
1
and the row electrode X
1
. As shown therein, during time period t
1
, a voltage pulse having a magnitude of V
1
is applied to row X
1
and a voltage pulse of −V
2
is applied to column electrode Y
1
. Typically, V
2
is approximately 1.6 volts. The resultant voltage at pixel 7
1,1
is −(V
1
-V
Iino Shoichi
Imamura Yoichi
Ito Akihiko
Mengistu Amare
Seiko Epson Corporation
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