Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-04-18
2002-12-03
Lao, Lun-Yi (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S058000, C345S060000
Reexamination Certificate
active
06489938
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a matrix display apparatus, and more particularly, to a plasma addressed display apparatus.
As one type of image display apparatuses, conventionally known is a plasma addressed display apparatus that includes a flat panel essentially composed of a display cell and a plasma cell laminated together and peripheral circuits such as a signal circuit and a vertical scanning circuit. One example of such a conventional plasma addressed display apparatus is described in Japanese Laid-Open Patent Publication No. 1-217396.
FIG. 22
shows a structure of a panel of a conventional plasma addressed display apparatus, which is a flat panel structure essentially composed of a display cell
1
and a plasma cell
2
laminated together with a microsheet
3
therebetween. The plasma cell
2
includes a glass substrate
4
and plasma discharge channels
5
arranged in rows, and generates plasma discharge line-sequentially for effecting scanning. The plasma discharge channels
5
are separated from the adjacent ones by barrier ribs
6
that define spaces arranged in rows. Stripe-shaped anode electrodes (A)
7
and stripe-shaped cathode electrodes (K)
8
are formed on the inner surface of the glass substrate
4
inside the respective plasma discharge channels
5
. Ionizable gas is enclosed in the spaces of the respective plasma discharge channels
5
.
The display cell
1
includes a liquid crystal layer
10
as a display medium retained between an upper glass substrate
9
and the microsheet
3
. Stripe-shaped color filters
12
and stripe-shaped data electrodes (P)
11
are formed on the inner surface of the glass substrate
9
in this order so as to extend in the direction intersecting with the plasma discharge channels
5
. Pixels are defined at the respective intersections of the color filters
12
and the data electrodes (P)
11
with the plasma discharge channels
5
forming a shape of matrix.
The operation of the plasma addressed display apparatus shown in
FIG. 22
will be described with reference to
FIG. 23
that shows a portion of
FIG. 22
in more detail. When a discharge pulse is applied, plasma discharge is generated in the plasma discharge channel
5
and the inside of the plasma discharge channel
5
is turned to and maintained at around an anode potential. In an equivalent circuit, a virtual electrode
20
is formed on the surface of the microsheet
3
inside the plasma discharge channel
5
and a switch
21
is turned on. A pulse application circuit
22
is a circuit for applying “video data” between the data electrode
11
and the anode electrode
7
. When the pulse application circuit
22
applies video data in synchronization with the generation of plasma discharge, video data is written in the liquid crystal layer
11
of the pixel via the microsheet
3
. When the plasma discharge is terminated, the switch
21
is turned off. The plasma discharge channel
5
is put in the floating state, allowing the written video data to be retained in the pixel. The transmittance of the liquid crystal changes depending on the retained video data.
In the plasma addressed display apparatus with the above construction, if higher resolution is intended, the components of the apparatus must be miniaturized both in the horizontal (row) and vertical (column) directions. In the case of enhancing the resolution in the vertical direction, the plasma discharge channels arranged in rows must be narrowed. In order to achieve this, the barrier ribs may be narrowed. However, extremely narrowing the barrier ribs is difficult from the standpoints of the fabrication technology and the mechanical strength. If the pitch of the barrier ribs is reduced while the width of the barrier ribs is kept unchanged, the aperture ratio will lower. Moreover, the viewing angle is narrowed since tilted incident light is blocked by the height of the barrier ribs.
The present inventor, together with other co-researchers, proposed a technique for enhancing the resolution of the plasma addressed display apparatus (Japanese Patent Application No. 10-253145, which, as well as corresponding U.S. patent application Ser. No. 09/391,804 filed on Sep. 8, 1999, are herein incorporated by reference). This technique attempts to enhance the vertical resolution of the plasma addressed display apparatus without changing the width and pitch of the barrier ribs.
FIG. 24
shows a panel structure of a plasma addressed display apparatus proposed by the present inventor and co-researchers described above. The plasma addressed display apparatus of
FIG. 24
is different from that of
FIG. 22
in that scanning electrodes (S)
13
are used as the electrodes for plasma discharge. The scanning electrodes (S)
13
are disposed at the bottoms of the barrier ribs
6
and at positions between the adjacent barrier ribs
6
.
The operation of the plasma addressed display apparatus will be described with reference to
FIGS. 25A and 25B
.
FIG. 25A
illustrates the video data write operation of the conventional plasma addressed display apparatus disclosed in the Japanese Laid-Open Patent Publication No. 1-217396 described above, and
FIG. 25B
illustrates the video data write operation of the high-definition plasma addressed display apparatus proposed by the present inventor and co-researchers (Japanese Patent Application No. 10-253145) employing a conventional drive method.
Referring to
FIG. 25A
, at timing T
11
, a discharge pulse is applied to a cathode K
1
, and video data D
11
is written and retained in a plasma discharge channel including the cathode K
1
and an anode A
1
. At timing T
12
as the next scanning period, a discharge pulse is applied to a cathode K
2
, and video data D
12
is written and retained in a plasma discharge channel including the cathode K
2
and an anode A
2
. At timing T
13
as the subsequent scanning period, video data D
13
is written in a similar manner. By this series of processing at timings T
11
through T
13
, predetermined video data are written in predetermined plasma discharge channels as shown under timing T
1
E. In this case, one piece of video data is written in one plasma discharge channel.
Referring to
FIG. 25B
, at timing T
21
, a discharge pulse is applied to a selected scanning electrode S
1
to allow plasma discharge to be generated between the selected scanning electrode S
1
and the adjacent scanning electrodes, i.e., between S
0
-S
1
and S
1
-S
2
, and video data D
21
is written and retained in a plasma discharge channel including the selected scanning electrode S
1
. At timing T
22
as the next scanning period, a discharge pulse is applied to a selected scanning electrode S
2
to allow plasma discharge to be generated between the selected scanning electrode S
2
and the adjacent scanning electrodes, i.e., in regions between S
1
-S
2
and S
2
-S
3
that are located in different plasma discharge channels blocked by the barrier rib
6
. Video data D
22
is written and retained in these plasma discharge channels. At this time, focusing on the video data written in the region between the scanning electrodes S
1
and S
2
, the video data D
21
written at timing T
21
is overwritten with the video data D
22
at timing T
22
. Similarly, at timings T
23
, T
24
, T
25
, and T
26
, a discharge pulse is applied to selected scanning electrodes S
3
, S
4
, S
5
, and S
6
, and video data D
23
, D
24
, D
25
, and D
26
are written and retained. By this series of processing at timings T
21
through T
26
, predetermined video data are written in predetermined plasma discharge channels as shown under timing T
2
E. In this way, in the plasma addressed display apparatus of
FIG. 24
, two pieces of video data are written in one plasma discharge channel. This improves the vertical resolution of the plasma addressed display apparatus, compared with the case shown in
FIG. 25A
, without changing the structure such as the pitch and width of the barrier ribs.
FIG. 26
shows the entire construction of the plasma addressed display apparatus shown in FIG.
24
. Referring to
Lao Lun-Yi
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
Sheng Tom V.
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