Matrix control circuit for a memory display

Details Matrix control circuit for a memory display Matrix control circuit for a memory display

1985-01-10

1987-06-09

Brigance, Gerald L.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340799, G09G 300

Patent

active

046723579

ABSTRACT:
Control circuit for memory type matrix display with k columns and r rows for k times r display elements, wherein each display element can have one of 2.sup.m brightness levels. This control circuit has a video memory for storing brightness information for the display element of each column. It comprises a column memory for each column. Each column memory including m column shift registers. Each column shift register having an input coupled to a corresponding information input for that column, and an output. A line time shift signal C.sub.s being applied to the shift pulse input of all column shift registers for shifting all column shift registers substantially at the end of each line time. The m output bits thus obtained are sequenced by means of a controlled gate circuit to produce a sequence of output bits at the information output of that column. This gate circuit is controlled such that each output bit lasts a predetermined part of the subsequent video line time.

REFERENCES:
patent: 4180813 (1979-12-01), Yoneda
patent: 4193095 (1980-03-01), Mizushima
patent: 4236154 (1980-11-01), Lee
patent: 4308534 (1981-12-01), Yamamoto
patent: 4353062 (1982-10-01), Lorteije et al.
patent: 4359730 (1982-11-01), Kunikane et al.
patent: 4427978 (1984-01-01), Williams
patent: 4488150 (1984-12-01), Kanatani

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