Matrix addressing circuitry and liquid crystal display...

Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix

Reexamination Certificate

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Details

C345S079000, C345S087000

Reexamination Certificate

active

07928948

ABSTRACT:
The invention aims at preventing an occurrence of artefacts while reducing power consumption. A matrix addressing method for alternately driving pixels. The frame period of the images is formed by successively sequencing on a time series a plurality of block periods, the block periods each being composed of a first half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with one polarity, the second half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with the other polarity. Ones of even-numbered row electrodes and odd-numbered row electrodes in arrangement order on the display screen are selected in the first half block. The others spatially adjoining the ones are selected in the second half block. A row electrode selecting order in the first half block and a row electrode selecting order in the second half block during one frame period are made differed from orders in the corresponding half blocks during the other frame period, respectively, so as to mitigate block-period-base visual artefact.

REFERENCES:
patent: 6496172 (2002-12-01), Hirakata
patent: 6717563 (2004-04-01), Kim
patent: 6724362 (2004-04-01), Min
patent: 10-59332 (1989-03-01), None
patent: 2000-250496 (2000-09-01), None
patent: 2002-244623 (2002-08-01), None
patent: 2004-004857 (2004-01-01), None
patent: WO 03/030137 (2003-04-01), None
patent: WO 03030137 (2003-04-01), None
PCT International Search Report of Counterpart PCT Application No. PCT/IB2005/052665.

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