Matrix addressable display with delay locked loop controller

Details Matrix addressable display with delay locked loop controller Matrix addressable display with delay locked loop controller

1996-10-03

1998-12-29

Brier, Jeffery

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

345100, 345205, 348540, 348541, G09G 336, G09G 500, H03L 700

Patent

active

058546154

ABSTRACT:
A matrix addressable display includes a delay locked loop formed from a delay chain formed from several variable delay blocks and a comparator. The delay locked loop receives a horizontal sync portion of an image signal and propagates the horizontal sync through the chain of delay blocks. The output of the last delay block drives the comparator that also receives an undelayed horizontal sync component. The comparator compares the undelayed horizontal sync to the delayed horizontal sync component and produces an error signal corresponding to the phase difference. The error signal is input to each of the delay blocks. In response to the error signal, the delay of the respective delay blocks increases or decreases to reduce the phase difference between the undelayed horizontal sync component and the delayed sync component. In addition to driving the delay chain, the horizontal sync component also walks a "1" through a row driver to sequentially activate rows of the array.

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