Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2002-07-30
2004-07-06
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S460000, C438S464000
Reexamination Certificate
active
06759276
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of separating created CMOS sensor image devices in such a way that foreign particles created as byproducts of the sawing operation do not contribute to yield loss of the separated devices.
(2) Description of the Prior Art
The art of creating CMOS base image sensor devices is well known and is in addition highlighted in considerable detail in the below referenced and related US Patents. Since this art does only indirectly apply to the invention and in view of the available literature on the subject of CMOS image sensor devices, no effort will be made at this time to provide further insight into the subject of creating CMOS image sensor devices.
CMOS image sensor devices are typically, like the majority of semiconductor devices that are created in a high volume and cost-effective manufacturing operation, created as multiple devices over the surface of one substrate. After the creation of these devices has been completed, the devices must be separated or singulated for further packaging of the devices. This process of singulation into individual chips is typically performed by sawing the wafer over the surface of which the devices have been created along scribe lines that have been provided over the surface of the substrate for this purpose. This process of sawing creates as a byproduct matter that is removed as a result of the sawing, which is essentially silicon based since it is the silicon substrate that is significantly affected by the sawing process.
The created byproduct of the sawing operation is not under control as far as distribution and scattering of this material is concerned. This leads to the creation of depositions of this byproduct not only where it is not desired but also where in addition it can have a severely negative impact on final product performance and acceptance. In short: the process of chip singulation by sawing of the wafer readily results in causing otherwise good chips to be contaminated with byproducts of the sawing process, which is a ready cause of final product failure. The invention addresses this concern and provides a method whereby a negative yield impact caused by byproducts of a singulation operation is eliminated.
U.S. Pat. No. 6,271,103 B1 (Lee) shows an UV Tape and die saw process for an image sensor.
U.S. Pat. No. 5,981,361 (Yamada) shows a dicing process.
U.S. Pat. No. 5,840,614 (Sim et al.) reveals a process using UV tape and lapping and sawing.
U.S. Pat. No. 5,641,714 (Yamanaka) discloses a process with tape.
U.S. Pat. No. 6,074,896 (Dando) shows a sawing process involving tape.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a method of singulating CMOS image sensor devices from a wafer over the surface of which these devices have been created.
Another objective of the invention is to eliminate the process of die singulation as a device yield detractor.
Yet another objective of the invention is to provide a method of controlling byproducts that are created during the processes of singulating die from a wafer.
A new method is provided of treating the wafer prior to the process of singulating the wafer into individual die. A surface of the wafer over which CMOS image sensor devices have been created is coated with a layer of material that is non-soluble in water. The wafer is singulated by sawing through the layer of material that has been coated over the surface of the wafer and by then sawing through the wafer. The singulated die is then further processed by applying steps of die mount, wire bonding, surrounding the die in a mold compound and marking the package.
REFERENCES:
patent: 5516728 (1996-05-01), Degani et al.
patent: 5641714 (1997-06-01), Yamanaka
patent: 5840614 (1998-11-01), Sim et al.
patent: 5981361 (1999-11-01), Yamada
patent: 6074896 (2000-06-01), Dando
patent: 6271103 (2001-08-01), Lee
patent: 6335224 (2002-01-01), Peterson et al.
Chang Chih-Kung
Hsiao Yu-Kung
Hsu Hung-Jen
Pan Sheng-Liang
Ackerman Stephen B.
Le Dung A.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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