Matching calibration for dual analog-to-digital converters

Details Matching calibration for dual analog-to-digital converters Matching calibration for dual analog-to-digital converters

2002-08-12

2003-05-20

Young, Brian (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S118000, C341S155000, C341S156000

Reexamination Certificate

active

06567022

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the conversion of analog signals to digital values and, more specifically to a calibration technique for matching the gain and offset characteristics of two analog-to-digital converters of the same type.
Analog-to-digital converters (ADCs) convert analog signals by sampling the signals and converting the samples into digital values. ADCs are used in a wide range of applications. In some applications, two or more ADCs are used in parallel with one another. In these applications, it is desirable for the gain and offset characteristics of each ADC to be the same as the characteristics of the other ADCs.
For example, two or more matched ADCs can be used to acquire two or more channels of analog data into a digital system. One of the most exacting applications that requires very closely matched gain and offset characteristics is when two or more ADCs are required to operate in an interleaved mode in order to provide digital data from an analog signal source at a higher speed than a single unit can convert. Such interleaved modes can be required in satellite and terrestrial data communication applications, for example. Each ADC preferably generates the same output value for a given analog input level. Any gain and offset differences between interleaved ADCs in these systems can cause data communication errors.
A technique is therefore desired for calibrating multiple ADCs simultaneously such that they have similar gain and offset characteristics, with a calibration performance that is acceptable in an interleaved mode of operation and all less exacting modes of operation.
SUMMARY OF THE INVENTION
One embodiment of the present invention is directed to a method for calibrating first and second analog-to-digital converters (ADCs). According to the method, a test signal is applied to the first and second ADCs. A first correction value is applied to an output of the first ADC to produce a first corrected output. A second correction value is applied to an output of the second ADC to produce a second corrected output. The first and second corrected outputs are then compared to identify a greater one and a lesser one of the first and second corrected outputs. At least one of the first and second correction values are adjusted relative to the other until the first or second corrected output that was identified as the lesser one exceeds the other.
Another embodiment of the present invention is directed to an analog-to-digital converter (ADC) system. The system includes a normal analog input, a test analog input, first and second ADCs, first and second correction circuits and a calibration circuit. The first ADC selectively operates on either the normal analog input or the test analog input and has a digital output. The second ADC selectively operates on either the normal analog input or the test analog input and has a digital output. The first correction circuit is adapted to modify the digital output of the first ADC by a first gain correction value and a first offset correction value to produce a first corrected output. The second correction circuit is adapted to modify the digital output of the second ADC by a second gain correction value and a second offset correction value to produce a second corrected output. The calibration control circuit has first and second comparison inputs coupled to the first and second corrected outputs, respectively, and generates the first and second gain correction values and the first and second offset correction values as a function of a comparison of the first and second corrected outputs.
Yet another embodiment of the present invention is directed to a multiple analog-to-digital converter (ADC) system. The system includes a normal analog input and a test analog input. First and second ADCs selectively operate on the normal analog input or the test analog input. First and second offset correction values and first and second gain correction values are applied to outputs of the first and second ADCS, respectively, to produce first and second corrected outputs, respectively. A first test signal level is applied to the analog test input, and at least one of the first and second offset correction values is repetitively adjusted relative to the other as a function of a comparison of the first and second corrected outputs. In addition, a second test signal level, which is different than the first test signal level, is applied to the analog test input and at least one of the first and second gain correction values is repetitively adjusted relative to the other as a function of a comparison of the first and second corrected outputs.


REFERENCES:
patent: 4143361 (1979-03-01), Tammes et al.
patent: 5164726 (1992-11-01), Bernstein et al.
patent: 5412385 (1995-05-01), Mangelsdorf
patent: 5818370 (1998-10-01), Sooch et al.
patent: 6516185 (2003-02-01), MacNally

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