Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2002-08-30
2003-12-23
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S118000
Reexamination Certificate
active
06667703
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the conversion of digital values to analog signals and, more specifically to a calibration technique for matching the gain and offset characteristics of two or more digital-to-analog converters of the same type.
Digital-to-analog converters (DACs) are used in a wide range of applications. In some applications, two or more DACs are used in parallel with one another. In these applications, it is desirable for the gain and offset characteristics of each DAC to be the same as the characteristics of the other DAC.
Two or more matched DACs are used in applications where two or more channels of digital data need to be converted into matched analog output levels. For example, matched DACs can be used to generate quadrature signals for satellite and terrestrial data communication systems. Each DAC preferably generates the same output level for a given digital input value. Any gain and offset differences between DACs in these systems can cause data communication errors.
A technique is therefore desired for calibrating multiple DACs simultaneously such that they have similar gain and offset characteristics.
SUMMARY OF THE INVENTION
One embodiment of the present invention is directed to a method for calibrating first and second digital-to-analog converters (DACs). According to the method, a first test value is applied to a test input. The test input is modified by a first correction value to produce a first corrected value, and the test input is modified by a second correction value to produce a second corrected value. The first and second corrected values are applied to first and second DACs, respectively to produce first and second corrected analog outputs. At least one of the first and second correction values is adjusted relative to the other as a function of the first and second corrected analog outputs.
Another embodiment of the present invention is directed to a DAC converter system, which has a normal input and a test input. A first correction circuit selectively modifies either the normal input or the test input by a first gain correction value and a first offset correction value to produce a first corrected value. A second correction circuit selectively modifies either the normal input or the test input by a second gain correction value and a second offset correction value to produce a second corrected value. A first DAC operates on the first corrected output and has a first analog output. A second DAC operates on the second corrected output and has a second analog output. A calibration control circuit has first and second inputs coupled to the first and second analog outputs, respectively, and generates the first and second gain correction values and the first and second offset correction values as a function of the first and second analog outputs.
Yet another embodiment of the present invention is directed to a multiple digital-to-analog converter (DAC) system. The system includes a normal input and a test input. A first set of offset and gain correction values are applied to either the digital normal input or the digital test input to produce a first corrected value. A second set of offset and gain correction values are applied to either the digital normal input or the digital test input to produce a second corrected value. First and second DACs operate on the first and second corrected values, respectively, and have first and second analog outputs, respectively. A digital value is applied to the test input, and at least one of the first and second offset correction values is repetitively adjusted relative to the other as a function of the first and second analog outputs. A second digital value, which is different than the first digital value, is applied to the digital test input and at least one of the first and second gain correction values is repetitively adjusted relative to the other as a function of the first and second analog outputs.
REFERENCES:
patent: 4222107 (1980-09-01), Mrozowski et al.
patent: 5121119 (1992-06-01), Higuchi et al.
patent: 5184062 (1993-02-01), Ladwig
patent: 5517191 (1996-05-01), Wynne
patent: 6351228 (2002-02-01), Kutsuno et al.
patent: 6489905 (2002-12-01), Lee et al.
patent: 6556154 (2003-04-01), Gorecki et al.
Block Stefan G.
Reuveni David R.
LSI Logic Corporation
Wamsley Patrick
Westman Champlin & Kelly
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