Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Utility Patent
1998-01-27
2001-01-02
Chin, Stephen (Department: 2734)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C370S335000, C375S143000
Utility Patent
active
06169771
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to filter circuits and in particular, to a matched filter for detecting the correlation between an input signal and a predetermined code sequence and to a filter circuit constituted by analog operation circuits.
BACKGROUND OF THE INVENTION
A Direct Sequence (DS) Spread Spectrum (SS) communication system performs acquisition which estimates within 1-chip, the timings of signal spread code sequences. It then synchronizes the operation of spread code generator in a receiver to the estimated timing.
There are two methods of performing this acquisition, namely by using (1) sliding correlators and (2) a matched filters.
Method (1) generates spread codes by roughly estimated timing and tries to receive them by gradual shifting. It multiplies a received signal and the spread code generated in the receiver and passes the result through a low-pass filter. Although the output of the low-pass filter has a large amplitude when phases of a received signal spread code and spread code being generated are identical, it has a low-level signal given by the auto-correlation function when the phases are not identical. Therefore, when the low-pass filter output is smaller than the predetermined level, the spread code phase generated by the spread code generator is slightly advanced or delayed. Repeating this identifies the phases of the transmission signal spread code and of the spread code generated in a receiver.
This method identifies phases by shifting the spread code generator phase by the time corresponding to one spread code cycle at most. When the spread code generator is working in a phase, it takes a single spread code cycle to ascertain if it is the correct phase. It means that this method needs the time of (one spread code cycle)×(spread code length) at most until acquisition is completed.
Method (2) detects correlation values using matched filter, which soon completes acquisition. When spread spectrum modulated signals are continuously input from the receiving side of a matched filter, every moment's correlation value appears in succession at the output side of the filter. Therefore, the correlation value peak can be detected by watching the matched filter outputs during one spread code cycle. Using this method completes acquisition in the time corresponding to one spread code cycle.
FIG. 5
shows an example of a conventional matched filter with a spread code length of N bits. In
FIG. 5
,
110
is an input terminal, and
120
1
to
120
N−1
are delay circuits for delaying input signals by unit time &tgr;. Delay circuits
120
1
to
120
N−1
are serially connected so that signals from
110
are sequentially delayed. Input signal X(t−i&tgr;), which is i&tgr; time before the present time, is output from
120
i
(i=1 to N−1) at the timing input terminal
110
receives signal X(t).
Numbers
130
0
to
130
N−1
show multiplication circuits which multiply signals X(t−i&tgr;) (i=0 to N−1) output from
110
or
120
1
to
120
N−1
and bit di (i=0 to N−1) corresponding to the spread code produced by a spread code generator (not shown). Bit di is +1 or −1. The received signal is output as it is when the bit corresponding to the spread code is +1, and it is output with inverted polarity when the bit is −1.
Outputs from
130
0
to
130
N−1
are added by adder
140
and output from output terminal
150
. This terminal
150
outputs correlation output Y(t) shown in Equation (1):
Y
(
t
)
=
∑
i
=
0
N
-
1
di
·
X
(
t
-
i
τ
)
(
1
)
Observing Y(t) during a single spread code cycle yields the correlation peak between the input signals and the spread codes, and rapid acquisition is thus possible.
To form a matched filter like this, an analog delay line using a charged couple device (CCD) or a surface acoustic wave (SAW) device, and a digital circuit in which the shift register works as a delay circuit by converting received signals into digital data are used.
Acquisition using a sliding correlator requires little electric power consumption per unit time, but takes a long time to complete. There is heavy power consumption when acquisition is continuous.
Acquisition using a matched filter is completed in a short time. When an analog matched filter is used, electric power consumption is small but computation accuracy varies. When a digital filter is used, the circuit size is large and electric power consumption is also large because many multiplications and additions have to be performed. With double sampling there is a larger sampling number and so a large circuit size, a serious problem affecting matched filter use in portable communication terminals.
On another point, a transversal filter is conventionally formed by discretely multiplying sequential sampled data by a predetermined coefficient and adding the products. Since this type of filter usually transfers analog signals sampled and held in sequence, the process stores analog data holding errors. To minimize these errors, a filter circuit which stores each coefficient in a cyclic shift register and circulates them instead of transferring the sampled analog data has been proposed in Japanese Patent Laid-Open Publication No. Hei 6-164320.
FIG. 15
shows an example of such a filter circuit. In
FIG. 15
, HG
1
is a first sample-and-hold circuit group including eight sample-and-hold circuits H
1
to H
8
, which are connected to input terminal Din, and HG
2
is a second sample-and-hold circuit group including eight sample-and-hold circuits H
9
to H
16
, which are connected to output D′in of multiplexer MUX. This system includes sixteen sample-and-hold circuits H
1
to H
16
. H
1
to H
16
sample and hold analog signals input from Din or D′in according to the predetermined sampling signals, and store the sampled data until the next sampled signals are supplied.
MUX is provided between HG
1
and HG
2
to select Din or the output of holding circuit Hout (described later) as D′in.
SR is the 16-stage of cyclic shift register, and each stage A
1
to A
16
stores the predetermined coefficients a
0
to a
15
that are to be multiplied by discrete analog input signals respectively sampled and held by H
1
to H
16
. The memory is sequentially circulated by sampling signals (not shown) and shift-clock synchronized to the sampling signals.
M
1
to M
16
are multiplication circuits, each of whose first input terminal receives a discrete signal from H
1
to H
16
, and whose other input terminal is connected to corresponding stage A
1
to A
16
, respectively. This configuration multiplies the discrete analog signals output from H
1
to H
16
by digital data a
0
to a
15
from A
1
to A
16
in M
1
to M
16
, respectively.
The multiplication results output from M
1
to M
16
are added in addition circuit AD, and their sum is output to holding circuit Hout. The output of Hout is also that of this filter circuit as well as another input of MUX.
The filter circuit having this structure works as described below when MUX connects Din and HG
2
.
H
1
to H
16
are sequentially driven by every sampling cycle to sample and store analog input signals from Din. That is, at the first sampling timing, H
1
is driven and the input signal then is sampled and held in H
1
. At the next sampling timing, H
2
is driven and the input signal then is sampled and held in H
2
. In this way, input signals are successively sampled and held in H
3
to H
16
at every sampling timing. After sampling data is held in H
16
, input signals are successively sampled and held from H
1
. Repeating this, all the necessary sequential data can be sampled and held by the predetermined timing without transferring data between sample-and-hold circuits.
When analog signals from Din are successively sampled and sixteen sequential data are held in H
1
to H
16
as above, coefficients a
0
to a
15
stored in SR and the sequential data in H
1
to H
16
are multiplied in M
1
to M
16
, resp
Motohashi Kazunori
Oin Xiaoling
Shou Guoliang
Takatori Sunao
Yamamoto Makoto
Chin Stephen
Pillsbury Madison & Sutro LLP
Rupert Paul N.
Yozan Inc.
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