Matched filter circuit

Details Matched filter circuit Matched filter circuit

1996-10-31

1998-08-04

Chin, Stephen

Pulse or digital communications

Repeaters

Testing

375208, 375355, 329304, H04B 1500

Patent

active

057905908

ABSTRACT:
The present invention has an object to provide a matched filter circuit which is possible to synchronize a spreading code with an input signal. A matched filter according to the present invention samples input signal in response to three clocks from the first to the third shifted by a half cycle of a sampling signal so as to judge whether the sampling clock is ahead or behind of the input signal according to signs of input signal sampled. One clock is selected to be the sampling clock.

REFERENCES:
patent: 4095226 (1978-06-01), Kratzar
patent: 5400368 (1995-03-01), Cheng et al.
patent: 5581579 (1996-12-01), Lin et al.
patent: 5654991 (1997-08-01), Andren et al.
Tanaka et al., "Development of Low Power Consumption LSI for SS Communication", Technical Report of IEICE, SST95-77, 1995-10.
Ogawa et al., "Development of 1 Chip SS Communication LSI Using Digital Matched Filters", Technical Report of IEICE, ISEC94-42, SST94-65, 1994-12.
Dual 64-TAP, 11 Mcps Digital Matched Filter/Correlator STEL-3310, Stanford Telecommunications, 1990.

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