Electrical computers: arithmetic processing and calculating – Electrical hybrid calculating computer – Particular function performed
Reexamination Certificate
1999-02-24
2002-05-14
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical hybrid calculating computer
Particular function performed
Reexamination Certificate
active
06389438
ABSTRACT:
DETAILED DESCRIPTION OF THE INVENTION
Background of the Invention
1. Field of the Invention
The present invention relates to a matched filter and signal reception apparatus. More particularly, the present application relates to a matched filter and a signal reception apparatus preferable for a DS-CDMA cellular system.
2. Description of Related Art
Direct sequence code division multiple access (DSCDMA) cellular systems have attracted more attention as the number of users of the land mobile communication have increased, based upon the large capacity of the DS-CDMA system. In the DS-CDMA system, at a transmitter side, transmission data is modulated and then spreaded by a PN-code. At a receiver side, the received signal is despread by the PN-code so that the transmission data is reproduced. A sliding correlator or a matched filter is used for the despreading. The sliding correlator is small in circuit size but requires a long time for the correlation calculation. While, the matched filter is fast in correlation calculation but is rather big in circuit size.
A conventional matched filter consists of a charge coupled device (CCD), a surface acoustic wave (SAW) device, or a digital circuit. A matched filter is proposed in Patent Publication Hei06-164320 by the inventors of the present invention, and consists of an analog circuit and is of high speed as well as low power consumption. The matched filter includes a sampling and holding circuit for holding a plurality of input analog signals as discrete data, a plurality of multiplication circuits for multiplying the analog signals by multipliers that are shifted and circulated, and an adder for summing the multiplied data.
However, the proposed matched filter has a problem with large circuit size because of the many analog sampling and holding circuits and peripheral circuits such as refreshing circuit.
SUMMARY OF THE INVENTION
The present invention provides a matched filter and a signal reception apparatus having a low power consumption and small circuit size.
In the present invention, a matched filter comprises an analog to digital converter for converting analog signals into digital data, a data holding means having a plurality of stages for holding said digital data, a multiplier supplying means for supplying a spreading code, a plurality of exclusive-OR circuits corresponding to the plurality of stages, each of which calculates an exclusive-OR of one of the digital data and one of said 1 bit data, and an adder for summing said exclusive-ORs.
In a matched filter according to the present invention, analog input data is converted to digital data by an analog to digital (A/D) converter and exclusive-OR of the digital data and PN-code is calculated.
In another embodiment of the matched filter of the present invention, analog input data is converted to digital data by an A/D converter and exclusive-OR of the digital data and PN-code is calculated, then the exclusive-or output is summed by an analog adder.
REFERENCES:
patent: 5930290 (1999-07-01), Zhou et al.
patent: 6064690 (2000-05-01), Zhou et al.
patent: 6169771 (2001-01-01), Shou et al.
patent: 8-84162 (1996-03-01), None
patent: 10-247955 (1998-09-01), None
patent: 11-168515 (1999-06-01), None
Mai Tan V.
Yozan Inc.
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