Matched filter

Details Matched filter Matched filter

1998-03-18

2001-03-27

Pham, Chi (Department: 2631)

Pulse or digital communications

Spread spectrum

Direct sequence

C375S150000, C327S091000

Reexamination Certificate

active

06208685

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an average value calculating circuit, and a correlation value calculating circuit, a matched filter and a communication device using the same.
2. Description of the Related Art
FIG. 8
is a schematic block diagram showing a prior art receiver for direct sequence (DS) spread spectrum communication.
A signal received by antenna
7
selectively passes through band-pass filter
8
and is provided to detecting circuit
9
. Detecting circuit
9
performs envelope or synchronous detection of the signal modulated according to ASK, FSK or PSK and converts it into analog or digital spread spectrum signal DIN. Matched filter
10
P calculates correlation value DOUT between spread spectrum signal DIN and a pseudorandom noise (PN). Determining circuit
11
determines the symbol duration for acquisition based on correlation value DOUT and obtains baseband data. To reduce the amount of data, if the baseband data are coded, for example, according to predictive coding, the baseband data are decoded by decoding circuit
12
. In the case of sound data, the output of decoding circuit
12
is converted into an analog value by digital-to-analog converter circuit
13
, and then, passes through low-pass filter
14
and is provided to speaker
15
. In the case of data such as image or text data, the output of the decoding circuit
12
is used as reproduction data.
The spread spectrum communication using such a receiver is superior to other communication schemes in interference wave excluding capability, concealability of the contents of communication and frequency use efficiency.
FIG. 9
shows the construction of conventional matched filter
10
P.
In digital or analog shift register
20
, delay elements DL
1
to DLn are cascaded. To the data input of delay element DL
1
, spread spectrum signal DIN is provided. In synchronization with clock CLK, input signals DIN and S
1
to Sn-i of delay elements DL
1
to DLn are held therein and they output delay signals S
1
to Sn. Delay elements DL
1
to DLn are flip-flops if spread spectrum signal DIN is digital, and are sample-and-hold circuits or CCDs, etc. if the spread spectrum signal DIN is analog.
Coincidence degrees D
1
to Dn between pseudorandom noise P
1
to Pn and delay signals S
1
to Sn are calculated by coincidence degree calculating circuits M
1
to Mn, respectively. Coincidence degree calculating circuits M
1
to Mn are, for example, multipliers if pseudorandom noise is 1 or −1, and are exclusive NOR gates if pseudorandom noise is a bit of ‘1’ or ‘0.’ Coincidence degrees D
1
to Dn are provided to adder circuit
21
and the sum total thereof is obtained as correlation value DOUT.
With such matched filter
10
P, correlation value DOUT is immediately obtained every clock period.
Pseudorandom noises vary from receiver to receiver. When the pseudorandom noise on the receiving side differ from that on the transmitting side, correlation value DOUT is always low, so that the received data cannot be decoded.
For example, for n=256, it is necessary to calculate the sum total of coincidence degrees D
1
to D
256
in one period of clock CLK. Consequently, construction of adder circuit
21
, the correlation value calculating circuit, the matched filter and the communication device is complicated.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide an average value calculating circuit having a simpler construction, and a correlation value calculating circuit, a matched filter and a communication device using the same.
In the 1st aspect of the present invention, as shown in
FIG. 1
for example, there is provided an average value calculating circuit comprising: a plurality of capacitors C
1
to Cn and a switching circuit
23
for sampling and holding charges corresponding to input signals D
1
to Dn to the capacitors C
1
to Cn respectively, and for connecting the capacitors C
1
to Cn in parallel while isolating the input signals D
1
to Dn to output average value corresponding to average voltage of the capacitors C
1
to Cn connected in parallel.
Defining that the voltages of the capacitors C
1
to Cn are V
1
to Vn when the charges corresponding to the input signals D
1
to Dn are held at the capacitors C
1
to Cn and that the voltages of the capacitors C
1
to Cn are DOUT when the capacitors are connected in parallel, since the sum total of the charges held in the capacitors C
1
to Cn is invariant before and after the parallel connection, the following equation holds:
C
1
·V
1
+C
2
·V
2
+ . . . +Cn·Vn=(C
0
+C
1
+ . . . +Cn)DOUT
DOUT is a weighted average value of voltages V
1
to Vn corresponding to the input signals D
1
to Dn with the weights of voltages V
1
to Vn being C
1
to Cn, respectively.
According to the 1st aspect of the present invention, since the average value calculating circuit is constituted by capacitors C
1
to Cn and switching circuit
23
, the construction is simpler than before. Thus, the present invention contributes to reduced manufacture cost of the average value calculating circuit, and the correlation calculating circuit, the matched filter and the communication device using the same.
In the 2nd aspect of the present invention, there is provided an average value calculating circuit as defined in the 1st aspect, wherein one end of each of the capacitors is supplied with a first reference potential, and wherein the switching circuit comprises: a plurality of first switching elements, each connected between a corresponding one of the inputs for receiving the input signals and the other end of a corresponding one of the capacitors; a common conductor; a plurality of second switching elements each connected between the other end of the corresponding one of the capacitors and the common conductor; and a resetting switching element with its one end connected to the common conductor and its other end supplied with a second reference potential, wherein when one of a first group consisting of the first switching elements and the resetting switching element, and a second group consisting of the second switching elements is on, the other thereof is off, substantially.
The 2nd reference potential may be equal to the 1st reference potential.
In the 3rd aspect of the present invention, there is provided an average value calculating circuit as defined in the 2nd aspect, wherein the capacitors comprise: a plurality of first capacitor elements each with its one end supplied with the first reference potential, its other end thereof being the other end of one of the capacitors; a plurality of second capacitor elements each with its one end supplied with a third reference potential; and a plurality of third switching elements each connected between the other end of the corresponding one of the first capacitor elements and the other end of corresponding one of the second capacitor elements.
The 3rd reference potential may be equal to the 1st reference potential.
According to the 3rd aspect of the present invention, by controlling on/off of the 3rd switching elements, the weights of the weighted average become variable.
In the 4th aspect of the present invention, there is provided a correlation value calculating circuit comprising: a coincidence degree calculating circuit for calculating degrees of coincidence between a parallel signal and a pseudorandom noise; a plurality of capacitors; and a switching circuit for sampling and holding charges corresponding to the degrees of coincidence to the capacitors and for connecting the capacitors in parallel while isolating the parallel signal to output average value corresponding to average voltage of the capacitors connected in parallel.
In the 5th aspect of the present invention, there is provided a matched filter comprising: a shift register having a plurality of cascaded delay elements, a first stage of the delay elements receiving a spread spectrum signal, the delay elements being clocked by a clock signal to provide a parallel signal

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