Match filter architecture based upon parallel I/O

Details Match filter architecture based upon parallel I/O Match filter architecture based upon parallel I/O

1999-07-09

2001-10-16

Ghebretinsae, Temesghen (Department: 2631)

Pulse or digital communications

Spread spectrum

Direct sequence

C708S301000, C708S314000

Reexamination Certificate

active

06304591

ABSTRACT:

SUMMARY OF THE INVENTION
The present invention is a match filter architecture that is used in the Spread ALOHA Multiple Access (SAMA) receiver to facilitate the separation of individual user's data from the incoming SAMA sample “chips” stream. The disclosures of U.S. Pat. Nos. 5,537,397 and 5,745,485 are hereby incorporated by reference.
The filter architecture is suitable for any digital filter with coefficients that are restricted to 0, +1, or −1. This filter architecture uses much less silicon and power than a comparable filter implemented in the conventional manner.
This filter architecture supports a very large number of taps by using a combined serial/parallel approach. It may operate at high speed and may be implemented with fewer gates than a typical filter design. Unlike a correlater, this filter outputs the convolution of the incoming signal with the coefficients at the same rate as the incoming chip samples, thus providing a means to detect more than one user within one pseudo-noise pattern interval.
The filter coefficients are limited to +/−1 or 0. The +/−1 filter coefficient taps correspond to the match code, typically a pseudo-noise code, and the 0-coefficient filter taps are placed in between the +/−1 taps to correspond to the over-sampling of the incoming signal.
The filter operates completely synchronously with a high frequency clock, which produces a high frequency signal. The clock is used to generate the sample (or chip) clock signal for control and synchronization of the sampling, the adding and the parallel output. The incoming chip samples from the parallel sample inputs are loaded into the delay shift register at the sample clock rate. The samples in the shift register are shifted to the right at the filter clock frequency at multiples of the sample rate. Each bit in the chip trickles down through the serial adders with one accumulator shift clock period of delay for each serial adder. At the final accumulator, the serial sum bits are collected for parallel presentation to the output registers at the sampling frequency. This approach works for any result where the number of bits in the output is less than or equal to the filter clock divided by the sample clock.
In the example shown, the bits in the shift register are shifted at a high frequency clock rate that is two (2) times the sampling rate. The serial adders operate at an accumulator shift rate that is a multiple of the sampling rate. Bits in the accumulator are shifted at the accumulator shift rate, and the convolution data in the accumulator is outputted at the sample rate.
These and further and other objects and features of the invention are apparent in the disclosure, which includes the above and ongoing written specification, with the claims and the drawings.


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IBM Technical Disclosure Bulletin, “Gate-Savings Approach to a Multi-Bit Correlator for a Spread Spectrum Communications System,” vol. 38, No. 6, Jun. 1995, pp. 653-656.

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