1984-08-24
1987-05-26
Larkins, William D.
357 41, 357 45, 357 68, H01L 2704
Patent
active
046689729
ABSTRACT:
A masterslice semiconductor device is provided, which reduces or eliminates unused transistors. In the basic cells of the masterslice semiconductor device, each transistor is formed as electrically independent from the others; i.e., each transistor has an individual gate electrode and has an individual region for the source and drain. Terminals formed in parallel to the gate channel of each transistor permits interconnection of the electrodes in a basic cell array using a straight wiring pattern. Such a straight interconnection reduces the effective number of wiring channels needed for a unit cell, and facilitates construction of a larger scale unit cell in a basic cell array.
REFERENCES:
patent: 4412237 (1983-10-01), Matsumura et al.
Electronics International, vol. 56, No. 3, Feb. 1983, "Gate Array Needs Fewer Gates for RAM", C. Cohen, pp. 86-87.
Goto Gensuke
Sato Shinji
Fujitsu Limited
Larkins William D.
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