Master slice type semiconductor integrated circuit having 2 or m

Details Master slice type semiconductor integrated circuit having 2 or m Master slice type semiconductor integrated circuit having 2 or m

1989-05-12

1990-07-17

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3073031, 307475, 364490, 357 45, H03K 1712

Patent

active

049423177

ABSTRACT:
An internal logic block is arranged in a chip body, and I/O cells and pads are arranged in a peripheral portion of the chip body. Three I/O cells are arranged for each pad.

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patent: 4819047 (1989-04-01), Gilfeather et al.
patent: 4825107 (1989-04-01), Naganuma et al.
patent: 4864381 (1989-09-01), Seefeldt et al.
patent: 4868630 (1989-09-01), Tanizawa et al.

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