Master slice type semiconductor integrated circuit device

Details Master slice type semiconductor integrated circuit device Master slice type semiconductor integrated circuit device

2006-07-05

2008-10-14

Wai-Sing, Louie (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

C257SE23010

Reexamination Certificate

active

07436007

ABSTRACT:
A plurality of terminals is formed in a basic cell. One terminal has first to fifth patterns. The first and second patterns are arranged to be spaced from each other. The third and fourth patterns are arranged to be spaced from each other, and are arranged so as to be adjacent to the first and second patterns. The fifth pattern is arranged between the first and second grid lines to interconnect the first to fourth patterns. A dimension of the fifth pattern in a direction of extension of a plurality of grid lines is set to be smaller than a dimension obtained by adding dimensions of the first and second patterns in the direction of extension of the grid lines to an interval of the both patterns, and a dimension obtained by adding dimensions of the third and fourth patterns to an interval of the both patterns.

REFERENCES:
patent: 5367187 (1994-11-01), Yuen
patent: 6603158 (2003-08-01), Kajii et al.
patent: 07-321210 (1995-12-01), None

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