Master-slice-type semiconductor integrated circuit device

Details Master-slice-type semiconductor integrated circuit device Master-slice-type semiconductor integrated circuit device

1984-09-24

1988-05-31

Larkins, William D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 40, 307467, H01L 2704

Patent

active

047484888

ABSTRACT:
A master-slice-type semiconductor integrated circuit device including basic cells, each having at least one logical circuit element, and current source cells for supplying current to the basic cells, each having at least one current source element and separated from the basic cells. A logic circuit operatively connects at least one logical circuit element in one of the basic cells and at least one current source element in one of the current source cells. The basic cells are arranged in groups extending in a lateral direction of the device and form cell rows in the lateral direction with groups of current source cells periodically formed in each cell row. The groups of current source cells in different cells rows are aligned in a longitudinal direction perpendicular to the lateral direction. The logic circuit is connected by conductive strips formed in wiring channels, each wiring channel being formed parallel and adjacent to at least one cell row.

REFERENCES:
patent: 3866066 (1975-02-01), Pedersen
patent: 3999214 (1976-12-01), Cass
patent: 4056810 (1977-11-01), Hart et al.
patent: 4336528 (1982-06-01), Kane
Review of Electrical Communication Laboratories, vol. 26, Nos. 9-10, Sep.-Oct. 1978, K. Wada et al. "Master-Slice Layout Design for Emitter Coupled Logic LSI" pp. 1355-1366.

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