Master slice type integrated circuit

Details Master slice type integrated circuit Master slice type integrated circuit

1988-02-12

1989-04-25

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3073031, 357 45, 364716, 364491, H03K 301, H03K 1901, H03K 1704, H01L 2700

Patent

active

048251070

ABSTRACT:
A master slice type integrated circuit for providing various circuits by altering the routing of interconnections comprises a plurality of input/output cells arranged in a peripheral region on a semiconductor chip, the input/output cells each comprising pads for connection with an external circuit, input wiring regions each for accommodating input interconnecting lines transmitting input signals applied to the pads, and output circuit regions each for forming output buffers; and a plurality of basic cells being arranged in a region on the chip surrounded by the arrangement of the input/output cells. Two adjacent input/output cells are paired with each other. The output circuit regions of the pair of the input/output cells are arranged in the vicinity of a boundary of the pair. The input wiring regions of the pair are arranged in the vicinity of boundaries with respect to other pairs.

REFERENCES:
patent: 4670749 (1987-02-01), Freeman
patent: 4697095 (1987-09-01), Fujii
patent: 4725835 (1988-02-01), Schreiner et al.
patent: 4727268 (1988-02-01), Hori
patent: 4734885 (1988-03-01), Luich

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