Master slice type integrated circuit

Details Master slice type integrated circuit Master slice type integrated circuit

1988-02-12

1989-06-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307469, 307451, 307465, H03K 326, H03K 19173

Patent

active

048374610

ABSTRACT:
A master slice type integrated circuit in which various circuits may be formed by varying the routing of interconnections, comprises a plurality of input/output cells being arranged in a peripheral region on a semiconductor chip; a plurality of basic cell columns each comprising a plurality of basic cells arranged in a predetermined direction, each basic cell constituting transistors; an interconnection region formed on the chip, for accommodating a data bus; and a plurality of latch cells being arranged in the basic cell columns, for keeping a potential of a data bus laid on the interconnection region to prevent the data bus from being changed into a floating state, each latch cell comprising transistors, each of which has a driving capability smaller than that of each transistor of the basic cell.

REFERENCES:
patent: 4760289 (1988-07-01), Eichelberger et al.
"N Channel Master Slice", by Kelly et al., IBM Technical Disclosure Bulletin, vol. 20, No. 11A, Apr. 1978.
"Layout of an Inter-Board Driver Circuit", by Vicary, IBM Technical Disclosure Bulletin, vol. 21, No. 4, Sep. 1978.

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